
Section 25 Electrical Characteristics
Rev. 4.00 Sep. 14, 2005 Page 910 of 982
REJ09B0023-0400
25.2 DC
Characteristics
Tables 25.3 and 25.4 list DC characteristics.
Table 25.3 DC Characteristics (1) [Common Items]
Conditions: Ta
=
−
40°C to
+
85°C
Item Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
Current
consumption
*
1
Normal operation
I
CC
*
2
— 300 400 mA
V
CC
= 1.8 V
I
φ
= 100 MHz
P
φ
= 33 MHz
I
CC
Q
*
3
—
10
20
mA V
CC
Q = 3.3 V
B
φ
= 50 MHz
Standby
mode
I
stby
*
2
— 200 1000
µ
A
I
stby
Q
*
3
—
5
20
µ
A
Sleep
mode
I
sleep
*
2
—
50
110 mA
Ta = 25
°
C
V
CC
Q = 3.3 V
V
CC
= 1.8 V
B
φ
= 50 MHz
P
φ
= 33 MHz
Input leakage
current
All input pins
|I
in
| — — 1.0
µ
A V
in
=
0.5 to V
CC
Q – 0.5 V
Three-state
leakage
current
All input/output pins,
all output pins
(except for pins with
weak keeper)
(off state)
|I
STI
| — — 1.0
µ
A
Vin =
0.5 to V
CC
Q – 0.5 V
Input
capacitance
All pins
C
in
— — 20 pF
Analog power
supply voltage
(A/D)
AV
CC
(AD) 3.0
3.3
3.6
V
During A/D
conversion
— 2 5 mA
Analog power
supply current
(A/D)
Idle
AI
CC
(AD)
— 600 1000
µ
A
Caution:
When the A/D converter is not in use, the AV
CC
and AV
SS
pins should not be open.
Note: 1. Current consumption values are when all output pins are unloaded.
2.
I
CC
I
sleep
and I
stby
, respectively, represents the total currents consumed in each Vcc, V
CC
(PLL1) and Vcc (PLL2)
3.
I
CC
Q and I
stby
Q, respectively, represents the total currents consumed in each V
CC
Q and
AV
CC
.
Summary of Contents for HD6417641
Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...
Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...
Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...
Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...
Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
Page 1035: ......
Page 1036: ...SH7641 Hardware Manual...