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Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 734 of 982
REJ09B0023-0400
Figure 19.11 shows the general format in synchronous serial communication.
Don't care
Don’t care
One unit of transfer data (character or frame)
Bit 0
Serial data
Synchronization
clock
Bit 1
Bit 3
Bit 4
Bit 5
LSB
MSB
Bit 2
Bit 6
Bit 7
*
*
Note:
*
High except in continuous transfer
Figure 19.11 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is output on the communication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial
clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the
MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In
synchronous mode, the SCIF transmits or receives data by synchronizing with the rising edge of
the serial clock.
Transmit/Receive Formats: The data length is fixed at eight bits. No parity bit can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input
from the SCK pin can be selected as the SCIF transmit/receive clock.
When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCIF is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs
while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive
FIFO data trigger number.
Transmitting and Receiving Data:
•
SCIF Initialization (Synchronous Mode)
Before transmitting, receiving, or changing the mode or communication format, the software must
clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF.
Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does
not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which
retain their previous contents.
Summary of Contents for HD6417641
Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...
Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...
Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...
Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...
Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
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