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Section 12 Bus State Controller (BSC)
Rev. 4.00 Sep. 14, 2005 Page 277 of 982
REJ09B0023-0400
12.3.4
Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the
external pin MD3 and memory size is listed in the table below.
Table 12.4 Correspondence between External Pin MD3 and Bus Width of Area 0
MD3
Bus Width of Area 0
0 16
bits
1 32
bits
12.4 Register
Descriptions
The BSC has the following registers. For the addresses and access sizes of these registers, see
section 24, List of Registers.
Do not access spaces other than CS0 until the termination of the setting the memory interface.
•
Common control register (CMNCR)
•
Bus control register for area 0 (CS0BCR)
•
Bus control register for area 2 (CS2BCR)
•
Bus control register for area 3 (CS3BCR)
•
Bus control register for area 4 (CS4BCR)
•
Bus control register for area 5A (CS5ABCR)
•
Bus control register for area 5B (CS5BBCR)
•
Bus control register for area 6A (CS6ABCR)
•
Bus control register for area 6B (CS6BBCR)
•
Wait control register for area 0 (CS0WCR)
•
Wait control register for area 2 (CS2WCR)
•
Wait control register for area 3 (CS3WCR)
•
Wait control register for area 4 (CS4WCR)
•
Wait control register for area 5A (CS5AWCR)
•
Wait control register for area 5B (CS5BWCR)
•
Wait control register for area 6A (CS6AWCR)
•
Wait control register for area 6B (CS6BWCR)
•
SDRAM control register (SDCR)
Summary of Contents for HD6417641
Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...
Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...
Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...
Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...
Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
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