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Section 13   Direct Memory Access Controller (DMAC) 

Rev. 4.00  Sep. 14, 2005  Page 440 of 982 

REJ09B0023-0400 

 

Bus Mode and Channel Priority Order: When channel 1 is transferring data in burst mode and a 
request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0 
will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer 
on channel 1 will only resume on completion of the transfer on channel 0. 

When channel 0 is in cycle steal mode, one transfer-unit of the data on this channel, which has the 
higher priority, is transferred. Data is then transferred continuously on channel 1 without releasing 
the internal bus. The bus will then switch between the two in this order: channel 1, channel 0, 
channel 1, channel 0, etc. That is, the bus state changes so that CPU cycles are for burst-mode 
transfer after the data transfer in cycle steal mode has been completed. An example of this is 
shown in figure 13.12. When multiple channels are in the burst mode, data transfer on the channel 
that has the highest priority is given precedence. When DMA transfer is being performed on 
multiple channels, bus mastership is not released to another bus-master device until all of the 
competing burst-mode transfers have been completed. 

CPU

DMA

CH1

DMA

CH1

DMA

CH0

DMA

CH1

DMA

CH0

DMA

CH1

DMA

CH1

CPU

CH0

CH1

CH0

 Cycle-steal mode in

DMAC CH0 and CH1

DMAC CH1

Burst mode

CPU

CPU

Priority: CH0 > CH1
CH0:     Cycle-steal mode  
CH1:     Burst mode 

DMAC CH1

Burst mode

 

Figure 13.12   Bus State when Multiple Channels Are Operating 

In the round-robin mode, do not mix channels in the cycle steal and burst modes. In this case, 
although the transfer operation on each channel will be performed correctly, switching between 
channels might not correctly follow the priority order. 

13.4.5 

Number of Bus Cycle States and 

DREQ

 Pin Sampling Timing 

Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states 
is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. 
For details, see section 12, Bus State Controller (BSC). 

DREQ 

Pin Sampling Timing: Figures 13.13 to 13.16 show the 

DREQ

 input sampling timings in 

each bus mode. 

Summary of Contents for HD6417641

Page 1: ...RISC engine Family SH7641 Series SH7641 HD6417641 Rev 4 00 REJ09B0023 0400 SH7641 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revi...

Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...

Page 3: ...a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting fr...

Page 4: ...pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing...

Page 5: ...ible for a defective product we will only offer after the agreement of both parties to exchange it with a new product from stock The following shows the robustness reference values of the LSI against...

Page 6: ...items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes i...

Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...

Page 8: ...LSI to the above users Refer to the SH 3 SH 3E SH3 DSP Software Manual for a detailed description of the instruction set Notes on reading this manual Product names The following products are covered...

Page 9: ...elated manuals are available from our web site Please ensure you have the latest versions of all documents you require http www renesas com eng SH7641manuals Document Title Document No SuperH RISC eng...

Page 10: ...ssor ESD Electrostatic discharge ECC Error checking and correction etu Elementary time unit FIFO First in first out Hi Z High impedance H UDI User debugging interface INTC Interrupt controller LSB Lea...

Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...

Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...

Page 13: ...44 2 4 Instruction Formats 48 2 4 1 CPU Instruction Addressing Modes 48 2 4 2 DSP Data Addressing 51 2 4 3 CPU Instruction Formats 58 2 4 4 DSP Instruction Formats 61 2 5 Instruction Set 67 2 5 1 CPU...

Page 14: ...quency Control Register FRQCR 149 4 5 Changing the Frequency 151 4 5 1 Changing the Multiplication Rate 151 4 5 2 Changing the Division Ratio 151 4 6 Notes on Board Design 152 Section 5 Watchdog Timer...

Page 15: ...s 182 7 2 1 Cache Control Register 1 CCR1 182 7 2 2 Cache Control Register 2 CCR2 183 7 3 Cache Operation 186 7 3 1 Searching Cache 186 7 3 2 Read Access 188 7 3 3 Prefetch Operation 188 7 3 4 Write A...

Page 16: ...0 9 5 Note on Initializing this LSI 216 9 6 Usage Notes 218 Section 10 Interrupt Controller INTC 219 10 1 Features 219 10 2 Input Output Pins 221 10 3 Register Descriptions 221 10 3 1 Interrupt Priori...

Page 17: ...gister BRSR 254 11 2 12 Branch Destination Register BRDR 255 11 3 Operation 256 11 3 1 Flow of the User Break Operation 256 11 3 2 Break on Instruction Fetch Cycle 257 11 3 3 Break on Data Access Cycl...

Page 18: ...ronous 386 12 5 11 Wait between Access Cycles 387 12 5 12 Bus Arbitration 399 12 5 13 Others 401 Section 13 Direct Memory Access Controller DMAC 405 13 1 Features 405 13 2 Input Output Pins 407 13 3 R...

Page 19: ...15 4 1 TAP Controller 468 15 4 2 Reset Configuration 469 15 4 3 TDO Output Timing 469 15 4 4 H UDI Reset 470 15 4 5 H UDI Interrupt 470 15 5 Boundary Scan 471 15 5 1 Supported Instructions 471 15 5 2...

Page 20: ...rt Register CMSTR 510 17 2 2 Compare Match Timer Control Status Register CMCSR 511 17 2 3 Compare Match Counter CMCNT 512 17 2 4 Compare Match Constant Register CMCOR 512 17 3 Operation 513 17 3 1 Int...

Page 21: ...omplementary PWM Mode 591 18 5 Interrupts 616 18 5 1 Interrupts and Priority 616 18 5 2 DMA Activation 618 18 5 3 A D Converter Activation 618 18 6 Operation Timing 619 18 6 1 Input Output Timing 619...

Page 22: ...tart Operation 641 18 8 3 Operation in Case of Re Setting Due to Error During Operation etc 642 18 8 4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation Etc...

Page 23: ...rupt Enable Register 1 USBIER1 755 20 3 8 USB Interrupt Enable Register 2 USBIER2 755 20 3 9 USBEP0i Data Register USBEPDR0i 756 20 3 10 USBEP0o Data Register USBEPDR0o 756 20 3 11 USBEP0s Data Regist...

Page 24: ...USB Bus Power Control Method 790 20 10 Notes on Usage 794 20 10 1 Receiving Setup Data 794 20 10 2 Clearing FIFO 794 20 10 3 Overreading or Overwriting Data Register 794 20 10 4 Assigning Interrupt So...

Page 25: ...1 4 Port D Control Register PDCR 828 22 1 5 Port E Control Register PECR 830 22 1 6 Port E I O Register PEIOR 832 22 1 7 Port E MTU R W Enable Register PEMTURWER 833 22 1 8 Port F Control Register PF...

Page 26: ...tion 24 List of Registers 865 24 1 Register Addresses by functional module in order of the corresponding section numbers 866 24 2 Register Bits 876 24 3 Register States in Each Operating Mode 896 Sect...

Page 27: ...ransceiver Timing 963 25 3 15 AC Characteristics Measurement Conditions 964 25 4 A D Converter Characteristics 965 Appendix 967 A Pin States 967 A 1 When Other Function is Selected 967 A 2 When I O Po...

Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...

Page 29: ...Data Transfer Addressing 54 Figure 2 14 Modulo Addressing 55 Figure 2 15 DSP Instruction Formats 61 Figure 2 16 Sample Parallel Instruction Program 89 Figure 2 17 Examples of Conditional Operations a...

Page 30: ...Section 5 Watchdog Timer WDT Figure 5 1 Block Diagram of the WDT 156 Figure 5 2 Writing to WTCNT and WTCSR 159 Section 6 Power Down Modes Figure 6 1 Canceling Standby Mode with STBCR STBY 173 Figure...

Page 31: ...12 13 Access Timing for MPX Space Address Cycle Wait 1 Data Cycle No Wait 333 Figure 12 14 Access Timing for MPX Space Address Cycle Access Wait 1 Data Cycle Wait 1 External Wait 1 334 Figure 12 15 Ex...

Page 32: ...gure 12 41 Example of Connection with 16 Bit Data Width Byte Selection SRAM 381 Figure 12 42 Burst MPX Device Connection Example 382 Figure 12 43 Burst MPX Space Access Timing Single Read No Wait or S...

Page 33: ...e 13 19 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection When DACK is Divided to 4 by Idle Cycles 447 Figure 13 20 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection...

Page 34: ...17 3 Count Timing 513 Figure 17 4 Timing of CMF Setting 514 Section 18 Multi Function Timer Pulse Unit MTU Figure 18 1 Block Diagram of MTU 520 Figure 18 2 Complementary PWM Mode Output Level Example...

Page 35: ...Figure 18 36 Example of PWM Cycle Updating 600 Figure 18 37 Example of Data Update in Complementary PWM Mode 601 Figure 18 38 Example of Initial Output in Complementary PWM Mode 1 602 Figure 18 39 Ex...

Page 36: ...ure 18 71 Conflict between TCNT Write and Clear Operations 628 Figure 18 72 Conflict between TCNT Write and Increment Operations 629 Figure 18 73 Conflict between TGR Write and Compare Match 630 Figur...

Page 37: ...in Phase Counting Mode Recovery in PWM Mode 1 661 Figure 18 103 Error Occurrence in Phase Counting Mode Recovery in PWM Mode 2 662 Figure 18 104 Error Occurrence in Phase Counting Mode Recovery in Pha...

Page 38: ...erial Data 736 Figure 19 14 Example of SCIF Transmit Operation 737 Figure 19 15 Sample Flowchart for Receiving Serial Data 1 738 Figure 19 16 Sample Flowchart for Receiving Serial Data 2 739 Figure 19...

Page 39: ...eration Single Mode Channel 1 Selected 806 Figure 21 3 Example of A D Converter Operation Multi Mode Channels AN0 to AN2 Selected 807 Figure 21 4 Example of A D Converter Operation Scan Mode Channels...

Page 40: ...us Timing for Normal Space One Cycle of Software Wait External Wait Cycle Valid WM Bit 0 No Idle Cycle 929 Figure 25 18 MPX IO Interface Bus Cycle Three Address Cycles One Software Wait Cycle One Exte...

Page 41: ...Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Bank Active Mode ACT WRITE Commands WTRCD 0 Cycle TRWL 0 Cycle 946 Figure 25 35 Synchronous DRAM Burst Write Bus Cycle Four Write Cycles Bank A...

Page 42: ...Bus Interface Input Output Timing 959 Figure 25 51 TCK Input Timing 960 Figure 25 52 TRST Input Timing Reset Hold State 961 Figure 25 53 H UDI Data Transfer Timing 961 Figure 25 54 Boundary Scan Inpu...

Page 43: ...a Transfer Instruction Formats 62 Table 2 15 Single Data Transfer Instruction Formats 63 Table 2 16 A Field Parallel Data Transfer Instructions 64 Table 2 17 B Field ALU Operation Instructions and Mul...

Page 44: ...f Local Data Move Operations 122 Table 3 14 Correspondence between Operands and Registers 123 Table 3 15 Address Value to be Stored into SPC 1 125 Table 3 16 Address Value to be Stored into SPC 2 126...

Page 45: ...Interrupt Exception Handling Sources and Priority 236 Section 11 User Break Controller UBC Table 11 1 Specifying Break Address Register 246 Table 11 2 Specifying Break Data Register 248 Table 11 3 Dat...

Page 46: ...e Normal Space Interface 389 Table 12 19 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode Transfer for the Normal Space Interface 390 Table 12 20 Minimum Number of Idl...

Page 47: ...3 and 4 525 Table 18 4 CCLR0 to CCLR2 Channels 1 and 2 525 Table 18 5 TPSC0 to TPSC2 Channel 0 526 Table 18 6 TPSC0 to TPSC2 Channel 1 526 Table 18 7 TPSC0 to TPSC2 Channel 2 527 Table 18 8 TPSC0 to T...

Page 48: ...le 18 43 Mode Transition Combinations 642 Table 18 44 Pin Configuration 675 Table 18 45 Pin Combinations 675 Section 19 Serial Communication Interface with FIFO SCIF Table 19 1 SCIF Pins 688 Table 19...

Page 49: ...d Write Operations PG7DT to PG0DT 858 Table 23 11 Port H Data Register PHDR Read Write Operations 862 Table 23 12 Port J Data Register PJDR Read Write Operations 863 Section 25 Electrical Characterist...

Page 50: ...l Appendix Table A 1 Pin States in Reset State Power Down Mode and Bus Released States When Other Function is Selected 967 Table A 2 Pin States in Reset State Power Down Mode and Bus Released States...

Page 51: ...different kinds of memory This LSI also supports powerful peripheral functions such as USB function and serial communication interface with FIFO 1 1 Features The features of this LSI are listed in tab...

Page 52: ...cess DSP data addressing modes increment indexing with or without modulo addressing Zero overhead repeat loop control Conditional execution instructions Clock pulse generator CPG Clock mode Input cloc...

Page 53: ...ry Three independent read write ports 8 16 32 bit access from the CPU Maximum two 16 bit accesses from the DSP 8 16 32 bit access from the DMAC Total memory 16 kbyte XRAM 8 kbyte YRAM 8 kbyte Interrup...

Page 54: ...to each area enables direct connection to SRAM SDRAM Burst ROM address data MPX mode supporting area exists Outputs chip select signal CS0 CS2 to CS4 CS5A B CS6A B for corresponding area selectable fo...

Page 55: ...r pulse unit MTU Maximum 16 pulse input output Selection of 8 counter input clocks for each channel The following operations can be set for each channel Waveform output at compare match Input capture...

Page 56: ...ing to the USB standard Corresponds mode of USB internal transceiver or external transceiver Supports control endpoint 0 balk transmission endpoint 1 2 interrupt endpoint 3 Supports USB standard comma...

Page 57: ...US I O port Legend ADC AUD BSC CACHE CMT CPG WDT CPU DMAC A D converter Advanced user debugger Bus state controller Cache memory Compare match timer Clock Pulse generator Watch dog Timer Central proce...

Page 58: ...pin assignments of this LSI is shown in figure 1 2 1 A B C D E F G H J K L M N P V W Y R T U A B C D E F G H J K L M N P V W Y R T U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9...

Page 59: ...lect 3 Port A F3 Vss Ground 0V E1 CS2 PTA 2 Chip select 2 Port A F4 Vcc Power supply 1 8V G2 UCLK PTB 0 USB external input clock Port B G3 VBUS PTB 1 USB power detection Port B F1 SUSPND PTB 2 USB sus...

Page 60: ...N1 AUDCK AUD clock M3 VccQ Power supply for I O circuits 3 3V M2 A25 PTA 14 Address bus Port A N4 AUDATA 0 PTJ 8 AUD data Port J P1 AUDATA 1 PTJ 9 AUD data Port J N3 AUDATA 2 PTJ 10 AUD data Port J N2...

Page 61: ...H W5 SCK1 PTH 5 Serial clock 1 Port H V5 CTS1 PTH 6 Transmit clear 1 Port H Y3 TxD1 PTH 7 Transmit data 1 Port H V4 RxD1 PTH 8 Receive data 1 Port H Y4 RTS1 PTH 9 Transmit request 1 Port H U5 SCK2 PTH...

Page 62: ...E V11 TIOC0B PTE 14 Timer input output 0B Port E W11 TIOC0A PTE 15 Timer input output 0A Port E U12 VssQ Ground for I O circuits 0V Y13 TCLKD PTF 8 Timer Clock Input D Port F V12 VccQ Power supply for...

Page 63: ...TG 3 A D converter input Port G 2 T18 AN 4 PTG 4 A D converter input Port G 2 V20 AN 5 PTG 5 A D converter input Port G 2 U18 AN 6 PTG 6 A D converter input Port G 2 U20 AVcc AD Power supply for A D 3...

Page 64: ...V J20 Vcc PLL1 Power supply for PLL 1 1 8V K18 Vss PLL1 Ground for PLL 1 0V K19 MD3 Bus width set for area 0 J17 MD2 Clock mode set H20 VccQ 1 Power supply for I O circuits 3 3V 1 J18 MD0 Clock mode s...

Page 65: ...TD 10 Data bus Port D B19 D25 PTD 9 Data bus Port D B18 D24 PTD 8 Data bus Port D B17 D23 PTD 7 Data bus Port D A19 D22 PTD 6 Data bus Port D B16 D21 PTD 5 Data bus Port D C16 D20 PTD 4 Data bus Port...

Page 66: ...A12 WE2 DQMUL D23 to D16 Select signal DQM SDRAM C11 Vss Ground 0V B11 CKE PTA 1 CK enable Port A D11 Vcc Power supply 1 8V A11 CASL PTA 4 CAS for Lower 32M byte address Port A A10 RASL PTA 6 RAS for...

Page 67: ...to high or low level when the pins are not driven externally Unused pins that are provided weak keeper circuits need not to be fixed their input levels Fix unused pins that are not provided weak keep...

Page 68: ...round pin Connect all VssQ pins to the system power supply 0V There will be no operation if any pins are open Vcc PLL1 I PLL1 power supply Power supply for the on chip PLL1 oscillator Vss PLL1 I PLL1...

Page 69: ...st Low when an external device requests the release of the bus mastership System control BACK O Bus mastership request acknowledge Indicates that the bus mastership has been released to an external de...

Page 70: ...23 to D16 when SDRAM is connected WE1 DQMLU O Byte specification Indicates that bits 15 to 8 of the data in the external memory or device are being written Selects D15 to D8 when SDRAM is connected WE...

Page 71: ...ions and data TDO O Test data output Serial output pin for instructions and data User debugging interface H UDI TRST I Test reset Initialization signal input pin AUDATA3 to AUDATA0 O AUD data Data out...

Page 72: ...apture input output compare output PWM output pins TIOC3A TIOC3B TIOC3C TIOC3D I O Input capture output compare match The TGRA_3 to TGRD_3 input capture input output compare output PWM output pins TIO...

Page 73: ...USB transceiver TXENL O Output enable Output enable pin to USB transceiver VBUS I USB power supply monitor USB cable connection monitor pin SUSPND O Suspend USB transceiver suspend state output pin UC...

Page 74: ...put output pins PTD15 to PTD0 I O General purpose port 16 bits general purpose input output pins PTE15 to PTE0 I O General purpose port 16 bits general purpose input output pins PTF15 to PTF0 I O Gene...

Page 75: ...ble with R0 to R7 banked to provide access to a separate set of R0 to R7 registers i e R0 to R7_BANK0 and R0 to R7_BANK1 depending on the value of the RB bit The register bank RB bit in the status reg...

Page 76: ...and restored from SPC in exception handling The system registers are MACH Multiply and accumulate high register MACL Multiply and accumulate low register PR Procedure register PC Program counter This...

Page 77: ...10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL VBR PR PC SPC 0 Notes 1 The R0 register is used as an index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode 2...

Page 78: ...1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0 to R15 Undefined Control registers SR RB bit 1 BL bit 1 I3 to I0 1111 H F The reserved bits other than bit 30 are...

Page 79: ...access Y memory R6 and R7 are used as the Y address register Ay and R9 is used as the Y index register Iy To access single data that uses the L bus R2 R3 R4 and R5 are used as the single data address...

Page 80: ...for Y data memory R9 Iy Index register for address register set Ay Single data transfer operation R2 to 5 As Address register set for memory R8 Is Index register for address register set As Figure 2 4...

Page 81: ...Ax R4 or R5 If DMY is 1 the modulo addressing mode is effective for the Y memory address pointer Ay R6 or R7 However both X and Y address pointers cannot be operated in modulo addressing mode even tho...

Page 82: ...ment modulo addressing for circular data buffering MOD holds the modulo start address MS and modulo end address ME In order to access RS RE and MOD load store control register instructions for these r...

Page 83: ...MOD STC RS RE MOD Rn STC L RS RE MOD Rn LDRS LDRE SETRC MOVS MOVX MOVY Pxxx are enabled DSP 0 All DSP instructions are treated as illegal instructions only SH3 instructions are supported DMY bit Modul...

Page 84: ...letion of exception handling Global base register GBR Stores base address of GBR indirect addressing mode The GBR indirect addressing mode is used for data transfer and logical operations on the on ch...

Page 85: ...d A1 include 8 guard bits fields A0G and A1G giving them a total width of 40 bits Three kinds of operation access the DSP data registers The first is DSP data processing When a DSP fixed point data op...

Page 86: ...be loaded or stored by this instruction comprise the upper 16 bits bits 31 to 16 for DSP registers except A0G and A1G When data is loaded into a register other than A0G and A1G in word mode the lower...

Page 87: ...t result Integer PDMSB Sign extended 24 bit result Cleared Logical PSHL Cleared 16 bit result Cleared Data transfer MOVS W Sign extended 16 bit data Cleared MOVS L Sign extended 32 bit data A0G A1G MO...

Page 88: ...SB PSHA 40 bit data Integer 24 bit data Logical PSHL PMULS 16 bit data MOVX Y W MOVS W 16 bit data Data transfer MOVS L 32 bit data A0G A1G MOVS W Data Data transfer MOVS L Data DSP Fixed point PDMSB...

Page 89: ...S 2 0 V N Z GT 8 31 0 a DSP Data Registers b DSP Status Register DSR Reset status DSR All zeros Others Undefined Figure 2 7 DSP Registers A0G 32 0 39 31 16 A0 A1 M0 M1 X0 X1 Y0 Y1 0 7 A1G DSR 16 bits...

Page 90: ...s its execution based on the DC bit This control affects only the operations in the DSP unit it controls the update of DSP registers only It cannot control operations in the CPU such as address regist...

Page 91: ...1 is smaller than operand 2 1 Operation result is negative or operand 1 is smaller than operand 2 4 Overflow bit V Indicates that the operation result has overflowed 1 Operation result has overflowed...

Page 92: ...into a register 31 0 Longword Figure 2 9 Longword Operand 2 2 2 DSP Type Data Formats This LSI has several different data formats that depend on the instruction This section explains the data formats...

Page 93: ...ard bits CPU type integer S Sign bit Longword Binary point Does not affect the operations Without guard bits With guard bits Without guard bits Multiplier input Shift amount for arithmetic shift PSHA...

Page 94: ...Address A 1 Address A 3 Big endian mode Figure 2 11 Byte Word and Longword Alignment 2 3 Features of CPU Core Instructions The CPU core instructions are RISC type instructions with the following featu...

Page 95: ...operation occurs after execution of the slot instruction However instruction execution for register updating etc excluding the branch operation is performed in delayed branch instruction delay slot in...

Page 96: ...e in memory The table in memory is referenced with an immediate data transfer instruction MOV using PC relative addressing mode with displacement Table 2 8 Immediate Data Referencing Type This LSI s C...

Page 97: ...referenced with a 16 or 32 bit displacement the displacement value is placed in a table in memory beforehand Using the method whereby immediate data is loaded when an instruction is executed this val...

Page 98: ...Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after...

Page 99: ...o extended Rn disp 1 2 4 Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 GBR indirect with disp...

Page 100: ...ord operand the lower 2 bits of PC are masked PC H FFFFFFFC 2 4 With longword operand disp zero extended PC disp 2 or PC H FFFFFFFC disp 4 Word PC disp 2 Longword PC H FFFFFFFC disp 4 PC relative disp...

Page 101: ...instructions MOVS W and MOVSL The data addressing is different for these two kinds of instructions An overview of the data transfer instructions is given in table 2 12 Table 2 12 Overview of Data Tran...

Page 102: ...increment 3 Increment address register addressing The Ax and Ay registers are address pointers After a data transfer they are each incremented by 2 post increment There is an index register for each...

Page 103: ...r With these instructions one of registers R2 to R5 is used as the single data transfer address register As The following four kinds of addressing can be used with single data transfer instructions 1...

Page 104: ...value reaches the preset modulo end address the address pointer value becomes the modulo start address Modulo addressing is only available for the X and Y data transfer instructions MOVX W and MOVY W...

Page 105: ...the X Y data transfer instruction the address pointer will not return to modulo start address MS even though the address register contents match ME Notes 1 Bits 1 to 15 of the address register are use...

Page 106: ...register R4 H A5007000 H A5007002 Place the data so that the upper 16 bits of the modulo start and end addresses are the same This is because the modulo start address overwrites only the lower 16 bits...

Page 107: ...else if not update Ay modulo Ay 2 or R9 Iy else if Operation is MOVS W or MOVS L if Addressing is Nop Inc Add index reg MAB As memory access cycle uses MAB The address to be used has not been updated...

Page 108: ...ta dddd Displacement Table 2 13 CPU Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0 NOP n type xxxx xxxx xxxx nnnn 15 0 nnn...

Page 109: ...irect nnnn register direct MOV L Rm Rn mmmm register direct nnnn pre decrement register indirect MOV L Rm Rn mmmm register direct nnnn indexed register indirect MOV L Rm R0 Rn md type xxxx dddd 15 0 m...

Page 110: ...ve with displacement R0 register direct MOVA disp PC R0 dddddddd PC relative BF label d12 type dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 type dddd nnnn xxxx 15 0 dd...

Page 111: ...gle data transfer instructions 16 bit length 2 Parallel processing instructions processed by the DSP unit 32 bit length The instruction formats are shown in figure 2 15 15 16 25 26 31 0 0 0 0 15 15 15...

Page 112: ...uction Formats Type Mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X memory NOPX 1 1 1 1 0 0 0 0 0 0 0 data MOVX W Ax Dx Ax Dx 0 0 1 transfer MOVX W Ax Dx 1 0 MOVX W Ax Ix Dx 1 1 MOVX W Da Ax Da 1 0 1...

Page 113: ...s Ix F A0G 1 1 Note Codes reserved for system use Parallel Processing Instructions Parallel processing instructions are provided for efficient execution of digital signal processing using the DSP unit...

Page 114: ...Y W Ay Dy MOVY W Ay Dy MOVY W Ay Iy Dy MOVY W Da Ay MOVY W Da Ay MOVY W Da Ay Iy Mnemonic X memory data transfer Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 115: ...shift Type 0 1 1 1 2 1 3 1 4 1 5 A1 6 1 7 A0 8 X0 9 X1 A Y0 B Y1 C M0 D 1 E M1 F 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 operand parallel instructions...

Page 116: ...Reserved if cc PSTS MACH Dz if cc PSTS MACL Dz if cc PLDS Dz MACH if cc PLDS Dz MACL 2 Reserved Reserved Mnemonic Type if cc 01 10 DCT 11 DCF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 117: ...ta transfer Immediate data transfer Peripheral module data transfer Structure data transfer 39 MOVA Effective address transfer MOVT T bit transfer SWAP Upper lower swap XTRCT Extraction of middle of l...

Page 118: ...BV Binary subtraction with underflow Logic 6 AND Logical AND 14 operation NOT Bit inversion instructions OR Logical OR TAS Memory test and bit setting TST Logical AND and T bit setting XOR Exclusive l...

Page 119: ...BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure RTS Return from subroutine procedure System 14 CLRT T bit clear 74 control CLRMAC MAC register clear in...

Page 120: ...Immediate data dddd Displacement 2 Indicates summary of operation Explanation of Symbols Transfer direction xx Memory operand M Q T Flag bits in SR Logical AND of each bit Logical OR of each bit Excl...

Page 121: ...nmmmm0001 Rm Sign extension Rn 1 MOV L Rm Rn 0110nnnnmmmm0010 Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm...

Page 122: ...R0 disp GBR 1 MOV W R0 disp GBR 11000001dddddddd R0 disp 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 1...

Page 123: ...h unsigned data 1 T 1 Comparison result CMP GE Rm Rn 0011nnnnmmmm0011 If Rn Rm with signed data 1 T 1 Comparison result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison resul...

Page 124: ...1 EXTU W Rm Rn 0110nnnnmmmm1101 A word in Rm is zero extended Rn 1 MAC L Rm Rn 0000nnnnmmmm1111 Signed operation of Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 2 5 1 MAC W Rm Rn 0100nnnnmmmm1111 Si...

Page 125: ...tion Instructions Instruction Instruction Code Operation Execution States T Bit AND Rm Rn 0010nnnnmmmm1001 Rn Rm Rn 1 AND imm R0 11001001iiiiiiii R0 imm R0 1 AND B imm R0 GBR 11001101iiiiiiii R0 GBR i...

Page 126: ...100101 T Rn T 1 LSB SHAD Rm Rn 0100nnnnmmmm1100 Rm 0 Rn Rm Rn Rm 0 Rn Rm MSB Rn 1 SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLD Rm Rn 0100nnnnmmmm1101 Rm 0 Rn Rm R...

Page 127: ...10001001dddddddd Delayed branch if T 1 disp 2 PC PC if T 0 nop 3 1 BT S label 10001101dddddddd If T 1 disp 2 PC PC if T 0 nop 2 1 BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 BRAF Rm 0000...

Page 128: ...0011110 Rm R1_BANK 4 LDC Rm R2_BANK 0100mmmm10101110 Rm R2_BANK 4 LDC Rm R3_BANK 0100mmmm10111110 Rm R3_BANK 4 LDC Rm R4_BANK 0100mmmm11001110 Rm R4_BANK 4 LDC Rm R5_BANK 0100mmmm11011110 Rm R5_BANK 1...

Page 129: ...1 LDS L Rm PR 0100mmmm00100110 Rm PR Rm 4 Rm 1 NOP 0000000000001001 No operation 1 PREF Rm 0000mmmm10000011 Rm cache 1 RTE 0000000000101011 Delayed branch SSR SPC SR PC 5 SETS 0000000001011000 1 S 1 S...

Page 130: ..._BANK Rn 1 STC L R5_BANK Rn 0100nnnn11010011 Rn 4 Rn R5_BANK Rn 1 STC L R6_BANK Rn 0100nnnn11100011 Rn 4 Rn R6_BANK Rn 1 STC L R7_BANK Rn 0100nnnn11110011 Rn 4 Rn R7_BANK Rn 1 STS MACH Rn 0000nnnn0000...

Page 131: ...en added to reduce the code size for the initial settings for zero overhead loop control An independent control register DSR is provided for the DSP engine This register is treated as a system registe...

Page 132: ...instructions are provided to set the repeat count in the RC field in SR 27 16 When an immediate operand type SETRC instruction is executed the 8 bit immediate operand data is set in SR 23 16 and 0 is...

Page 133: ...Rn 1 LDS L Rn DSR 0100nnnn01100110 Rn DSR Rn 4 Rn 1 LDS L Rn A0 0100nnnn01110110 Rn A0 Rn 4 Rn 1 LDS L Rn X0 0100nnnn10000110 Rn X0 Rn 4 Rn 1 LDS L Rn X1 0100nnnn10010110 Rn X1 Rn 4 Rn 1 LDS L Rn Y0 0...

Page 134: ...uctions cannot be used with these 16 bit instructions In single transfer the Ax pointer and two other pointers are used as the As pointer but the Ay pointer is not used Tables 2 26 and 2 27 list the s...

Page 135: ...MSW of Dx 0 LSW of Dx Ax Ix Ax 1 MOVX W Da Ax 111100A D 1 01 MSW of Da Ax 1 MOVX W Da Ax 111100A D 1 10 MSW of Da Ax Ax 2 Ax 1 MOVX W Da Ax Ix 111100A D 1 11 MSW of Da Ax Ax Ix Ax 1 NOPY 111100 0 0 0...

Page 136: ...MOVS W Ds As 111101AADDDD0101 MSW of Ds As 1 MOVS W Ds As 111101AADDDD1001 MSW of Ds As As 2 As 1 MOVS W Ds As Is 111101AADDDD1101 MSW of Ds As As Is As 1 MOVS L As Ds 111101AADDDD0010 As 4 As As Ds 1...

Page 137: ...s a pointer address that indicates a memory address Table 2 28 Correspondence between DSP Data Transfer Operands and Registers Register Ax Ix Dx Ay Iy Dy Da As Ds R0 CPU registers R1 R2 As2 Yes R3 As3...

Page 138: ...transfer instructions described in section 2 6 3 Single and Double Data Transfer for DSP Data Instructions but has a special function in load instructions B field data operation instructions are of th...

Page 139: ...R4 NOPY Figure 2 16 Sample Parallel Instruction Program Square brackets mean that the contents can be omitted The no operation instructions NOPX and NOPY can be omitted Table 2 31 gives an overview of...

Page 140: ...y Dz 111110 10110001xxyyzzzz Sx Sy Dz 1 DCT PADD Sx Sy Dz 111110 10110010xxyyzzzz If DC 1 Sx Sy Dz If DC 0 nop 1 DCF PADD Sx Sy Dz 111110 10110011xxyyzzzz If DC 0 Sx Sy Dz If DC 1 nop 1 PSUB Sx Sy Dz...

Page 141: ...0010xxyyzzzz If DC 1 Sy 0 Sx Sy Dz logical shift If DC 1 Sy 0 Sx Sy Dz If DC 0 nop 1 DCF PSHL Sx Sy Dz 111110 10000011xxyyzzzz If DC 0 Sy 0 Sx Sy Dz logical shift If DC 0 Sy 0 Sx Sy Dz If DC 1 nop 1 P...

Page 142: ...If DC 0 nop 1 DCF PDMSB Sx Dz 111110 10011111xx00zzzz If DC 0 normalization count shift value Sx Dz If DC 1 nop 1 DCF PDMSB Sy Dz 111110 1011111100yyzzzz If DC 0 normalization count shift value Sy Dz...

Page 143: ...nop 1 POR Sx Sy Dz 111110 10110101xxyyzzzz Sx Sy Dz 1 DCT POR Sx Sy Dz 111110 10110110xxyyzzzz If DC 1 Sx Sy Dz If DC 0 nop 1 DCF POR Sx Sy Dz 111110 10110111xxyyzzzz If DC 0 Sx Sy Dz If DC 1 nop 1 P...

Page 144: ...00yyzzzz If DC 0 Sy 31 16 1 Dz If DC 1 nop 1 PCLR Dz 111110 100011010000zzzz h 00000000 Dz 1 DCT PCLR Dz 111110 100011100000zzzz If DC 1 h 00000000 Dz If DC 0 nop 1 DCF PCLR Dz 111110 100011110000zzzz...

Page 145: ...111111010000zzzz Dz MACL 1 DCT PLDS Dz MACL 111110 111111100000zzzz If DC 1 Dz MACL 1 DCF PLDS Dz MACL 111110 111111110000zzzz If DC 0 Dz MACL 1 PADDC Sx Sy Dz 111110 10110000xxyyzzzz Sx Sy DC Dz Carr...

Page 146: ...otherwise 0 1 1 Overflow mode The DC bit is set if the result of an ALU or shift PSHA arithmetic operation exceeds the destination register range excluding the guard bits and is cleared otherwise When...

Page 147: ...OVY W A0 R6 R9 When condition is True Before execution After execution X0 H 33333333 Y0 H 55555555 A0 H 123456789A R4 H 00008000 R6 H 00008233 R9 H 00000004 R4 H 1111 R6 H 2222 X0 H 11110000 Y0 H 5555...

Page 148: ...OPX and NOPY instruction codes are shown in table 2 33 Table 2 33 Examples of NOPX and NOPY Instruction Codes Instruction Code PADD X0 Y0 A0 MOVX W R4 X0 MOVY W R6 R9 Y0 1111100000001011 1011000100000...

Page 149: ...e base precision and 8 bits of the guard bit parts So the signed bit is copied to the guard bit parts when a register not providing the guard bit parts is specified as the source operand When a regist...

Page 150: ...ll 0 All 0 Dz Table 3 2 Correspondence between Operands and Registers Register Sx Sy Dz Du A0 Yes Yes Yes A1 Yes Yes Yes M0 Yes Yes M1 Yes Yes X0 Yes Yes Yes X1 Yes Yes Y0 Yes Yes Yes Y1 Yes Yes As sh...

Page 151: ...Carry or Borrow Mode CS 2 0 000 The DC bit indicates that carry or borrow is generated from the most significant bit of the operation result except the guard bit parts Some examples are shown in figu...

Page 152: ...ative Value Mode Zero Value Mode CS 2 0 010 The DC flag indicates whether the operation result is 0 or not When the result is 0 the DC bit shows 1 When it is not 0 the DC bit shows 0 Overflow Mode CS...

Page 153: ...a signed is greater than or equal to the source 2 data signed as the result of compare operation PCMP So a PCMP operation should be executed in advance when a conditional operation is executed under t...

Page 154: ...teger Arithmetic Operation Flow Table 3 3 Variation of ALU Integer Operations Mnemonic Function Source 1 Source 2 Destination PINC Increment by 1 Sx 1 Dz 1 Sy Dz PDEC Decrement by 1 Sx 1 Dz 1 Sy Dz No...

Page 155: ...ource and destination operand is not used in order to generate them See section 3 1 1 ALU Fixed Point Operations for details In case of a conditional operation they are not updated even though the spe...

Page 156: ...y updated in accordance with the operation result In case of a conditional operation they are not updated even though the specified condition is true and the operation is executed In case of an uncond...

Page 157: ...the same state as the DC bit set in signed greater than mode by the CS 2 0 bits See the signed greater than mode part above 3 1 4 Fixed Point Multiply Operation Figure 3 8 shows the multiply operatio...

Page 158: ...n in figure 3 8 In the SH s standard multiply operations the lower words of both source operands are input into a MAC unit The operation result is also different from the SH s case The SH s multiply o...

Page 159: ...Arithmetic shift with immediate Dz Imm1 Dz PSHL Imm2 Dz Logical shift with immediate Dz Imm2 Dz Note 32 Imm1 32 16 Imm2 16 Arithmetic Shift Figure 3 9 shows the arithmetic shift operation flow DSR GT...

Page 160: ...peration is executed In case of an unconditional operation they are always updated in accordance with the operation result The definition of the DC bit is selected by the CS 2 0 condition selection bi...

Page 161: ...rce 2 operand can be specified by either the register or immediate operand The available shift range is from 16 to 16 Here a negative value means the right shift and a positive value means the left sh...

Page 162: ...3 1 6 Most Significant Bit Detection Operation The PDMSB most significant bit detection operation is used to calculate the shift amount for normalization Figure 3 11 shows the PDMSB operation flow an...

Page 163: ...efinition of the DC bit is selected by the CS0 to CS2 condition selection bits in DSR The DC bit result is 1 Carry or Borrow Mode CS 2 0 000 The DC bit is always cleared 2 Negative Value Mode CS 2 0 0...

Page 164: ...0 28 0 0 0 0 0 0 0 1 All 0 All 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 All 0 All 0 0 0 0 0 0 1 1 0 0 0 0 0 1 All 0 All 0 0 0 0 0 0 0 0 0 0 0 0 1 All 1 All 1 1 1 1 1 1 1 1 0 0 0 1 All 1 All 1 1 1 1 1 1 0 2 0 1...

Page 165: ...case of providing guard bit parts it rounds from 40 bits to 24 bits When a round instruction is executed H 00008000 is added to the source operand data and then the lower word is cleared Figure 3 12 s...

Page 166: ...w 0 H 00 0002 H 00 0001 H 00 0001 8000 H 00 0002 0000 H 00 0002 8000 Rounded result Analog value True value Figure 3 13 Definition of Rounding Operation Table 3 10 Variation of Rounding Operation Mnem...

Page 167: ...y Operation Table 3 12 shows the definition of overflow protection for integer arithmetic operations When an SH s standard multiply or MAC operation is executed the S bit function is completely the sa...

Page 168: ...Y memory Both of these data transfer operations cannot be executed for one memory A load instruction for X memory can specify either the X0 or X1 register as a destination operand and for a load instr...

Page 169: ...s type of operation but Y pointers are not available This type of operation can access any memory address space and all registers in the DSP unit except for DSR can be specified for both source and de...

Page 170: ...instruction is possible since DSR is defined as a system register LAB 31 0 LDB 15 0 2 0 2 R8 Pointer R2 R3 R4 R5 Any memory areas Not affected for store and cleared for load See description of A0G and...

Page 171: ...R8 Pointer R2 R3 R4 R5 Any memory areas Cannot be specified X0 X1 Y0 Y1 M0 M1 A0G A1G A0 A1 DSR Figure 3 16 Single Data Transfer Operation Flow Longword All data transfer operations are executed in th...

Page 172: ...uction PLDS PSTS Cannot be used X0 X1 MACH MACL Y0 Y1 M0 M1 A0 A1 A0G A1G DSR Figure 3 17 Local Data Move Instruction Flow Table 3 13 Variation of Local Data Move Operations Mnemonic Function Operand...

Page 173: ...Iy Dy Sx Sy Du Se Sf Dg Sx Sy Dz A0 1 2 2 1 1 A1 1 2 1 1 2 1 1 M0 1 1 1 1 M1 1 1 1 1 X0 2 1 2 1 1 1 2 X1 2 1 1 1 2 Y0 2 1 2 1 1 1 2 DSP Registers Y1 2 1 1 1 2 Notes 1 Registers available for operands...

Page 174: ...a repeat loop Repeat end register RE keeps the repeat end address There are some exceptions See note Actual Implementation Options Repeat counter RC keeps the number of repeat times In order to perfor...

Page 175: ...LDRE must be executed before SETRC 3 In a case that the repeat loop has four or more instructions in it stall cycles are necessary according to the pipeline state at execution 4 If a repeat loop has l...

Page 176: ...at the repeat top instr1 7 If a repeat loop has four or more instructions in it any PC relative instructions MOVA disp PC R0 etc don t work properly at two instructions from the bottom of the repeat...

Page 177: ...after execution An exception is accepted at neither instruction B nor C but the request is saved and is accepted just before the next instruction A or B is to be executed The address of this next inst...

Page 178: ...nstr3 instr4 A B C C C A Figure 3 18 Restriction of Interrupt Acceptance in Repeat Loop Note 1 Actual Implementation Repeat start and repeat end registers RS and RE specify the repeat start instructio...

Page 179: ...C RptCount RptStart0 instr0 RptStart instr1 Repeated instruction instr2 CASE 2 2 Repeated Instructions LDRS RptStart0 6 LDRE RptStart0 4 SETRC RptCount RptStart0 instr0 RptStart instr1 Repeated instru...

Page 180: ...loop sequences However for easy programming an extended instruction REPEAT is provided to handle these complex labeling and offset issues Details will be described in the following note 2 Note 2 Exte...

Page 181: ...instr1 Repeated instruction instr2 CASE 2 2 Repeated Instructions REPEAT RptStart RptEnd RptCount instr0 RptStart instr1 Repeated instruction 1 RptEnd instr2 Repeated instruction 2 CASE 3 3 Repeated I...

Page 182: ...ruction N 2 instrN 1 Repeated instruction N 1 RptEnd instrN Repeated instruction N instrN 1 The expanded results of each case corresponds to the same case numbers in note 1 3 2 2 DSP Data Addressing T...

Page 183: ...1 DS A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Destination registers Dx X0 X1 Dy Y0 Y1 Ds A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Addressing for MOVX W and MOV W This LSI can access X and Y data memories simultaneously...

Page 184: ...ess to X and Y data memories are 16 bit data width Therefore the increment operation adds 2 to an address register To realize decrement set 2 in an index register and use add index register operation...

Page 185: ...MX and DMY in SR are used for the modulo addressing control If DMX is 1 the modulo addressing mode is effective for the X memory address pointer Ax R4 or R5 If the DMY is 1 it is effective for the Y m...

Page 186: ...ll not return to modulo start address MS even though the address register contents match ME Notes 1 Bits 1 to 15 of the address register are used for comparison Though ME retains its previous value fo...

Page 187: ...ss register MOVX W R4 Dx R4 H A5007000 H A5007002 Place the data so that the upper 16 bits of the modulo start and end addresses are the same This is because the modulo start address overwrites only t...

Page 188: ...en updated Ax is one of R4 5 if DMX 0 DMX 1 DMY 1 Ax Ax 2 or R8 Ix or 0 Inc Index Not Update else if not update Ax modulo Ax 2 or R8 Ix Ay is one of R6 7 if DMY 0 Ay Ay 2 or R9 Iy or 0 Inc Index Not U...

Page 189: ...if AddrReg 15 1 ME 15 1 AddrReg 15 1 MS 15 1 else AddrReg AddrReg Index return AddrReg X and Y Data Transfer Instructions MOVX W and MOVY W This type of instruction uses the XDB and the YDB to access...

Page 190: ...on Instruction code for Y data transfer operation Control for X memory Control for Y memory Input output control for DSP data registers X0 X1 A0 A1 Input output control for DSP data registers Y0 Y1 A0...

Page 191: ...flict between data access and instruction fetch The single data transfer instruction has word and longword access modes Figure 3 23 shows a block diagram of single data transfer The existing CPU core...

Page 192: ...LDB else Ds 7 0 LDB 7 0 Ds is A0G or A1G else Store if Ds A0G Ds A1G LDB 15 0 Ds 31 16 Ds is A0G or A1G else LDB 15 0 Ds 7 0 with 8bit sign extension else if MA NLS W L is long word access MOVS L if L...

Page 193: ...input on the external clock signal line is used Three clocks generated independently An internal clock I for the CPU and cache a peripheral clock P for the on chip peripheral modules a bus clock B CKI...

Page 194: ...STBCR STBCR2 STBCR3 STBCR4 Legend Frequency control register Standby control register Standby control register 2 Standby control register 3 Standby control register 4 Peripheral clock P Bus clock B C...

Page 195: ...ock operating mode Divider The divider generates a clock signal at the operating frequency used by the internal or peripheral clock The operating frequency can be 1 1 2 1 3 or 1 4 times the output fre...

Page 196: ...k input output pin CKIO I O Clock output pin The pin can also be placed in the high impedance state Input for the external clock pulse Clock output pin CKIO2 Output Low level output or clock output pi...

Page 197: ...used in mode 7 Table 4 3 Relationship between Clock Mode and Frequency Range PLL frequency multiplier Selectable frequency ranges MHz Clock operating mode FRQCR register setting PLL Circuit 1 PLL Circ...

Page 198: ...ON 4 OFF 4 1 1 20 to 25 20 to 25 80 to 100 20 to 25 20 to 25 H 1313 ON 4 OFF 2 1 1 20 to 33 33 20 to 33 33 40 to 66 66 20 to 33 33 20 to 33 33 H 1333 ON 4 OFF 1 1 1 20 to 33 33 20 to 33 33 20 to 33 3...

Page 199: ...e The previous value is also retained when an internal reset is triggered by an overflow of the WDT Bit Bit Name Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0...

Page 200: ...write value should always be 0 5 4 IFC1 IFC0 0 0 R W R W Internal Clock Frequency Division Ratio These bits specify the frequency division ratio of the internal clock with respect to the output frequ...

Page 201: ...ired value in the STC1 and STC0 bits The division ratio can also be set in the IFC 1 0 and PFC 1 0 bits 4 The processor pauses temporarily and the WDT starts incrementing The internal and peripheral c...

Page 202: ...ks When external clocks are input from the EXTAL pin leave the XTAL pin open In order to prevent a malfunction due to the reflection noise caused in a signal line which connected to XTAL pin cut this...

Page 203: ...n width must be as wide as possible to reduce inductive interference In clock operating mode 7 the EXTAL pin is pulled up and the XTAL pin is left open Since the analog power supply pins of the PLL ar...

Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...

Page 205: ...a watchdog timer or interval timer 5 1 Features The WDT has the following features Can be used to ensure the clock settling time The WDT is used in leaving standby mode or the temporary periods on sta...

Page 206: ...Registers for the addresses and access sizes of these registers Watchdog timer counter WTCNT Watchdog timer control status register WTCSR 5 2 1 Watchdog Timer Counter WTCNT The watchdog timer counter...

Page 207: ...e Use a byte access to read the WTCSR Note The WTCNT differs from other registers in the prevention of erroneous writes See section 5 2 3 Notes on Register Access for details Bit Bit Name Initial Valu...

Page 208: ...KS0 0 0 0 R W R W R W Clock Select These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock P The overflow period that is shown insid...

Page 209: ...ddress H A415FF86 WTCSR write Figure 5 2 Writing to WTCNT and WTCSR 5 3 Use of the WDT 5 3 1 Canceling Standbys The WDT can be used to cancel standby mode with an interrupt such as an NMI interrupt Th...

Page 210: ...for the counter in the WTCNT counter These values should ensure that the time till count overflow is longer than the clock oscillation settling time 3 When the frequency control register FRQCR is writ...

Page 211: ...terval timer or watchdog timer mode 1 Timer tolerance After timer operation has started the period from the power on reset point to the first count up timing of the WTCNT varies depending on the time...

Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...

Page 213: ...to reduced power consumption These modes are canceled by a reset or interrupt 6 1 Features 6 1 1 Power Down Modes This LSI has the following power down modes and function 1 Sleep mode 2 Standby mode 3...

Page 214: ...retained Specified module halts Refreshed automati cally 1 Clear MSTP bit to 0 with the exception of the MSTP bits for the USB module set these bits 2 Power on reset Note The pin state is retained or...

Page 215: ...S1 Processing state 0 STATUS0 Output Indicates the operational state of this LSI HH Manual reset HL Sleep mode LH Standby mode LL Normal operation Power on reset RESETP Input Inputting low level signa...

Page 216: ...TBCR The standby control register STBCR is an 8 bit readable writable register that specifies the state of the power down mode This register is initialized to H 00 by a power on reset but retains its...

Page 217: ...STP10 0 R W Module Stop 10 When the MSTP10 bit is set to 1 the supply of the clock to the H UDI is halted 0 H UDI runs 1 Clock supply to H UDI halted 6 MSTP9 0 R W Module Stop 9 When the MSTP9 bit is...

Page 218: ...tandby Control Register 3 STBCR3 STBCR3 is a readable writable 8 bit register used to select whether or not individual modules operate in power down mode STBCR3 is initialized to H 00 by a power on re...

Page 219: ...be 0 3 MSTP33 0 R W Module Stop 33 When the MSTP33 bit is set to 1 supply of the clock to the ADC stops 0 The ADC runs 1 Supply of the clock to the ADC stops 2 MSTP32 0 R W Module Stop 32 When the MST...

Page 220: ...module stops 1 Supply of the clock to the USB is started 5 MSTP45 0 R W Module Stop 45 When the MSTP45 bit is set to 1 supply of the clock to the MTU stops 0 The MTU runs 1 Supply of the clock to the...

Page 221: ...value read is not defined Clock pulses continue to be output on the CKIO and CKIO2 pins In sleep mode a high signal and low signal are output from the STATUS1 and STATUS0 pins respectively 2 Cancelin...

Page 222: ...s Retaining Data Interrupt controller INTC All registers On chip clock pulse generator CPG All registers User break controller UBC All registers Bus state controller BSC All registers A D converter AD...

Page 223: ...the WTCNT reaches H 80 A manual reset will not be accepted while the STBY bit is set Interrupts are accepted in standby mode even when the BL bit in the SR register is 1 If necessary save SPC and SSR...

Page 224: ...ng the corresponding MSTP bit to 1 cancels the module standby state When taking a module out of the module standby state by clearing the corresponding bit to 0 or setting it to 1 in the case of the US...

Page 225: ...L STATUS1 Low STATUS0 Low 4 Bcyc Bus clock cycle Notes 3 3 2 0 to 30 Bcyc 4 0 Bcyc to normal reset normal 1 4 RESETM Figure 6 2 STATUS Output at Manual Reset 2 Standby Mode A Standby mode is canceled...

Page 226: ...standby LH STATUS1 Low STATUS0 High normal LL STATUS1 Low STATUS0 Low Bcyc Bus clock cycle Oscillation stops Reset Notes 2 4 3 normal standby reset 1 0 to 20 Bcyc 5 4 normal RESETM Figure 6 4 STATUS O...

Page 227: ...ATUS 1 RESETM must be kept low until STATUS reset 2 reset HH STATUS1 High STATUS0 High 3 sleep HL STSTUS1 High STATUS0 Low 4 normal LL STATUS1 Low STATUS0 Low 5 Bcyc Bus clock cycle Notes 4 4 1 2 0 to...

Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...

Page 229: ...the address space is partitioned into five subdivisions and the cache access method is determined by the address Table 7 2 shows the kind of cache access available in each address space subdivision Ta...

Page 230: ...Data array ways 0 to 3 LRU Figure 7 1 Cache Structure Address Array The V bit indicates whether the entry data is valid When the V bit is 1 data is valid when 0 data is not valid The U bit indicates w...

Page 231: ...ate the way to be replaced in case of a cache miss The relationship between LRU and way replacement is shown is table 7 3 when the cache lock function is not used 1 concerning the case where the cache...

Page 232: ...to 4 must always be cleared to 0 CCR1 is initialized to H 00000000 by a power on or manual reset and retain the previous value by standby mode module standby mode and sleep mode Bit Bit Name Initial...

Page 233: ...R2 The relationship between the setting of each bit and a way to be replaced when the prefetch instruction is executed are listed in table 7 4 On the other hand when the prefetch instruction is execut...

Page 234: ...K 0 0 R W R W Way 3 Load Way 3 Lock When a cache miss occurs by the prefetch instruction while W3LOAD 1 and W3LOCK 1 in cache locking mode the data is always loaded into way 3 Under any other conditio...

Page 235: ...e same time Table 7 5 Way to be Replaced when a Cache Miss Occurs in Other than PREF Instruction Cache Locking Mode Bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced 0 Decided by LRU table 7 3 1 0 0...

Page 236: ...he cache is enabled CE bit in CCR register is 1 whenever instructions or data in spaces of P0 P1 and P3 are accessed the cache will be searched to see if the desired instruction or data is in the cach...

Page 237: ...ys 0 to 3 Data array ways 0 to 3 31 12 11 4 3 2 1 0 Address CMP0 CMP1 CMP2 CMP3 Physical address Legend CMP0 Comparison circuit for way 0 CMP1 Comparison circuit for way 1 CMP2 Comparison circuit for...

Page 238: ...re not modified No instructions or data is transferred to the CPU Prefetch Miss No instructions or data is transferred to the CPU The way to be replaced follows table 7 4 Other operations are the same...

Page 239: ...During the write back cycles the cache can be accessed The write back buffer can hold one line of cache data 16 bytes and its physical address Figure 7 3 shows the configuration of the write back buff...

Page 240: ...to 4 W for selecting the way bits 13 and 12 A for specifying the existence of associates operation and H F0 to indicate address array access bits 31 to 24 In W bits 13 and 12 00 is way 0 01 is way 1 1...

Page 241: ...entry corresponding to the way 1 Address array access a Address specification Read access Write access b Data specification both read and write accesses 2 Data array access both read and write accesse...

Page 242: ...n entry in the address array is set to 0 the entry is written back if the entry s U bit is 1 An example when a write data is specified in R0 and an address is specified in R1 is shown below R0 H 0110...

Page 243: ...s The Y memory resides in addresses H 05017000 to H 05018FFF in space P0 or addresses H A5017000 to H A5018FFF 8 kbytes in space P2 The X RAM is divided into page 0 and page 1 according to the address...

Page 244: ...F H 05610000 H 07FFFFFF H 05000000 H 05007000 H 05008000 H 05009000 H 0500FFFF H 05010000 H 05017000 H 05018000 H 05019000 H 0501FFFF Figure 8 1 X Y Memory Address Mapping 8 3 X Y Memory Access from D...

Page 245: ...e is on access must be performed from space P2 non cacheable space Operation during access from space P0 cannot be guaranteed When the cache is off spaces P0 and P2 can both be used Specify the P2 are...

Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...

Page 247: ...defined exception processing routine and executing the process to support the above functions are called exception handling This LSI has two types of exceptions general exceptions and interrupts The...

Page 248: ...EVT2 10 9 2 1 0 31 12 11 0 0 0 0 0 31 12 11 0 Figure 9 1 Register Bit Configuration 9 1 1 TRAPA Exception Register TRA TRA is assigned to address H FFFFFFD0 and consists of the 8 bit immediate data im...

Page 249: ...as 0 The write value should always be 0 11 to 0 EXPEVT R W 12 Bit Exception Code Note Initialized to H 000 at power on reset and H 020 at manual reset 9 1 3 Interrupt Event Register 2 INTEVT2 INTEVT2...

Page 250: ...ion event is written to bits 11 to 0 of the exception event EXPEVT or interrupt event INTEVT2 register 6 If a TRAPA instruction is executed an 8 bit immediate data specified by the TRAPA instruction i...

Page 251: ...C for details of the exception codes for interrupt requests Table 9 1 lists exception codes for resets and general exceptions 9 2 4 Exception Request and BL Bit Multiple Exception Prevention The BL bi...

Page 252: ...and the instruction address is saved to the SPC After returning from the exception processing program execution resumes from the instruction where the exception was accepted In a processing completio...

Page 253: ...slot illegal instruction exceptions re execution type unconditional trap processing completion type 5 An exception related to data access CPU address error re execution type 6 Unconditional trap proc...

Page 254: ...100 Completed User breakpoint After instruction execution address 2 5 Ignored H 1E0 H 00000100 User breakpoint Data break I BUS break 2 5 Ignored H 1E0 H 00000100 General exception events Completed DM...

Page 255: ...set Conditions Manual reset is request Operations Set EXPEVT to H 020 initialize the CPU and on chip peripheral modules and branch to the reset vector H A0000000 For details refer to the register desc...

Page 256: ...1 4n 3 Word data is accessed from addresses other than word boundaries 4n 1 4n 3 Long word is accessed from addresses other than longword boundaries 4n 1 4n 2 4n 3 The area ranging from H 80000000 to...

Page 257: ...guaranteed Types Instruction synchronous re execution type Save address An instruction address where an exception occurs Exception code H 180 Remarks None Illegal slot instruction Conditions When und...

Page 258: ...ore instruction execution Instruction synchronous re execution type Operand break L bus Instruction synchronous processing completion type Data break L bus Instruction asynchronous processing completi...

Page 259: ...struction following the instruction where a break occurs a delayed branch instruction destination address if an instruction is assigned to a delay slot Exception code H 5C0 Remarks An exception occurs...

Page 260: ...eat counter is 1 or more In this section this period is called the repeat control period The following shows program examples where the number of instructions in the repeat loop are 4 or more 3 2 and...

Page 261: ...s an instruction three instructions before a repeat end instruction RptDtct1 C1 RptDtct2 C2 RptEnd RptDtct3 C2 Repeat end instruction InstrNext A Example 2 Repeat loop consisting of three instructions...

Page 262: ...rior to a repeat start instruction RptStart RptEnd RptDtct1 C1 Repeat start instruction Repeat end instruction InstrNext A SPC Saved by an Exception in Repeat Control Period If an exception is accepte...

Page 263: ...at an instruction in the hatched areas above a return address to be saved in the SPC is incorrect If SR RC 11 0 is 1 or 0 a correct return address is saved in the SPC Illegal Instruction Exception in...

Page 264: ...ss controller DMAC until the CPU can accept a request User break before instruction execution A user break before instruction execution is accepted at instruction B and an address of instruction B is...

Page 265: ...nstructions some restrictions apply to repeat detection instructions and all the remaining instructions In a repeat loop consisting of four or more instructions restrictions apply to only the three in...

Page 266: ...s LSI needs to be initialized by a software reset before the power is turned on Execute the following program immediately after a power on reset Note that the following program overwrites contents of...

Page 267: ...ould overwrite the general registers on the CPU 3 Do not modify these codes MOV L H A5007000 R4 MOV L H A5008000 R5 MOV L H A5017000 R6 MOV L H A5018000 R7 MOV L R4 R0 MOV L R5 R0 MOV L R6 R0 MOV L R7...

Page 268: ...is executed However note that the correct operation cannot be guaranteed if a re execution type exception occurs 2 In an instruction assigned at a delay slot of the RTE instruction a user break canno...

Page 269: ...be set By setting the ten interrupt priority registers the priorities of on chip peripheral modules and IRQ interrupts can be selected from 16 levels for individual request sources NMI noise canceler...

Page 270: ...r debugging interface IIC2 ICR IPR IMR IMCR IRR0 SR I2C interface 2 Interrupt control register Interrupt priority registers B to J Interrupt mask registers 0 to 10 Interrupt mask clear registers 0 to...

Page 271: ...register addresses and register states during each processing refer to section 24 List of Registers Interrupt control register 0 ICR0 Interrupt control register 1 ICR1 Interrupt control register 3 IC...

Page 272: ...ster 10 IMR10 Interrupt mask clear register 0 IMCR0 Interrupt mask clear register 1 IMCR1 Interrupt mask clear register 2 IMCR2 Interrupt mask clear register 3 IMCR3 Interrupt mask clear register 4 IM...

Page 273: ...ers are initialized to H 0000 by a power on reset or manual reset but are not initialized in standby mode Bit Bit Name Initial Value R W Description 15 14 13 12 IPR15 IPR14 IPR13 IPR12 0 0 0 0 R W R W...

Page 274: ...MTU0 V MTU1 A B MTU1 V U IPRH MTU2 A B MTU2 V U MTU3 A B C D MTU3 V IPRI MTU4 A B C D MTU4 V POE IIC2 IPRJ DMAC0 DMAC1 DMAC2 DMAC3 Note Reserved These bits are always read as 0 The write value should...

Page 275: ...Sets the level of the signal input at the NMI pin This bit can be read from to determine the NMI pin level This bit cannot be modified 0 NMI input level is low 1 NMI input level is high 14 to 9 All 0...

Page 276: ...upt pins enabled 1 Use of pins IRQ7 to IRQ0 as interrupt pins disabled 13 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 10 9 8 7 6 5 4 3 2 1 0 IRQ51S IRQ50S...

Page 277: ...e R W Description 15 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 2 1 0 IRQ71S IRQ70S IRQ61S IRQ60S 0 0 0 0 R W R W R W R W IRQn Sense Select These bits s...

Page 278: ...ial Value R W Description 7 6 5 4 3 2 1 0 IRQ7R IRQ6R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W IRQn Interrupt Request Indicates whether there is interrupt re...

Page 279: ...To prevent this set IMR0 to IMR9 while no interrupts are set to be generated and then read the new settings from these registers Table 10 3 shows the relationship between IMR and each interrupt sourc...

Page 280: ...RI1 RxI1 ERI1 ADC0 ADC0 ADC0 ADC0 SCIF1 SCIF1 SCIF1 SCIF1 IMR4 ITI WDT WDT WDT WDT IMR5 TxI2 BRI2 RxI2 ERI2 ADI1 USIHP USI1 USI0 SCIF2 SCIF2 SCIF2 SCIF2 ADC1 USB USB USB IMR6 TCI2U TCI2V TGI2B TGI2A T...

Page 281: ...hip peripheral module interrupts Table 10 4 shows the relationship between IMCR and each interrupt source Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 IMC7 IMC6 IMC5 IMC4 IMC3 IMC2 IMC1...

Page 282: ...ADC0 ADC0 ADC0 SCIF1 SCIF1 SCIF1 SCIF1 IMCR4 ITI WDT WDT WDT WDT IMCR5 TxI2 BRI2 RxI2 ERI2 ADI1 USIHP USI1 USI0 SCIF2 SCIF2 SCIF2 SCIF2 ADC1 USB USB USB IMCR6 TCI2U TCI2V TGI2B TGI2A TCI1U TCI1V TGI1...

Page 283: ...from sleep mode or standby mode with an NMI interrupt 10 4 2 H UDI Interrupt The H UDI interrupt is accepted between one instruction and another when the H UDI interrupt command section 15 4 5 H UDI I...

Page 284: ...controller DMAC Serial communication interfaces SCIF0 to SCIF2 A D converters ADC0 and ADC1 Compare match timers CMT0 and CMT1 USB function module USB Multifunction timer pulse units MTU0 to MTU4 Watc...

Page 285: ...is assigned a unique code by INTEVT2 The start address of the interrupt service routine is common for each interrupt source This is why for instance the value of INTEVT2 is used as an offset at the st...

Page 286: ...H 660 0 to 15 0 IPRC 15 to 12 IRQ4 H 680 0 to 15 0 IPRD 3 to 0 IRQ5 H 6A0 0 to 15 0 IPRD 7 to 4 IRQ6 H 6C0 0 to 15 0 IPRD 11 to 8 IRQ7 H 6E0 0 to 15 0 IPRD 15 to 12 DMAC0 DEI0 H 800 0 to 15 0 IPRJ 15...

Page 287: ...3 to 0 High TCI1U H C60 Low MTU2 TGI2A H C80 0 to 15 0 IPRH 15 to 12 High TGI2B H CA0 Low TCI2V H CC0 IPRH 11 to 8 High TCI2U H CE0 Low MTU3 TGI3A H D00 0 to 15 0 IPRH 7 to 4 High TGI3B H D20 TGI3C H...

Page 288: ...and sends an interrupt request signal to the CPU 4 Detection timing The INTC operates and notifies the CPU of interrupt requests in synchronization with the peripheral clock P The CPU receives an int...

Page 289: ...erated SR BL 0 or sleep mode Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No NMI Level 15 interrupt Set interrupt sourse in INTEVT2 Save SR to SSR save PC to SPC Set BL RB bits in SR to...

Page 290: ...the interrupt 6 Execute the RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 Figure 10...

Page 291: ...independent or sequential condition on channels A and B sequential break setting channel A and then channel B match with break conditions but not in the same bus cycle Address Comparison bits are mask...

Page 292: ...equest UBC Location CCN Location LDB IDB XDB YDB Legend BBRA BARA BAMRA BASRA BBRB BARB BAMRB BASRB BDRB BDMRB BETR BRSR BRDR BRCR Break bus cycle register A Break address register A Break address mas...

Page 293: ...er B BARB Break address mask register B BAMRB Break bus cycle register B BBRB Break data register B BDRB Break data mask register B BDMRB Break control register BRCR Execution times break register BET...

Page 294: ...ot included in the break condition Note n 31 to 0 11 2 3 Break Bus Cycle Register A BBRA Break bus cycle register A BBRA is a 16 bit readable writable register which specifies 1 L bus cycle or I bus c...

Page 295: ...ition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R W R W Read Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition 00 Condit...

Page 296: ...ak condition in channel B If the I bus or L bus is selected in BBRB an IAB or LAB address is set in BAB31 to BAB0 If the X memory is selected in BBRB the values in bits 15 to 1 in XAB are set in BAB31...

Page 297: ...11 2 6 Break Data Register B BDRB BDRB is a 32 bit readable writable register The control bits CDB1 CDB0 XYE and XYS in BBRB select one of the four data buses for break condition B Bit Bit Name Initi...

Page 298: ...Data Mask Register B BDMRB BDMRB is a 32 bit readable writable register BDMRB specifies bits masked in the break data specified by BDRB Bit Bit Name Initial Value R W Description 31 to 0 BDMB31 to BDM...

Page 299: ...t this bit setting is enabled only when the L bus is selected with the CDB1 and CDB0 bits Selection between the X memory bus and Y memory bus is done by the XYS bit 0 Selects L bus for the channel B b...

Page 300: ...ition is the instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R W R W Read Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition 00 Condit...

Page 301: ...ng a variety of break conditions Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 SCMFCA 0 R W L Bus Cycle Con...

Page 302: ...0 In order to clear this flag write 0 into this bit 0 The I bus cycle condition for channel B does not match 1 The I bus cycle condition for channel B matches 11 PCTE 0 R W PC Trace Enable 0 Disables...

Page 303: ...ct Selects two conditions of channels A and B as independent or sequential conditions 0 Channels A and B are compared under independent conditions 1 Channels A and B are compared under sequential cond...

Page 304: ...t read only register BRSR stores bits 27 to 0 in the address of the branch source instruction BRSR has the flag bit that is set to 1 when a branch occurs This flag bit is cleared to 0 when BRSR is rea...

Page 305: ...re not initialized by a power on reset The eight BRDR registers have a queue structure and a stored register is shifted at every branch Bit Bit Name Initial Value R W Description 31 DVF 0 R BRDR Valid...

Page 306: ...ition match flags SCMFCA SCMFDA SCMFCB and SCMFDB can be used to check if the set conditions match or not The matching of the conditions sets flags but they are not reset 0 must first be written to th...

Page 307: ...is set to 1 11 3 2 Break on Instruction Fetch Cycle 1 When L bus instruction fetch read word or longword is set in the break bus cycle register BBRA or BBRB the break condition becomes the L bus inst...

Page 308: ...data access cycle address and the comparison condition for each operand size is listed in table 11 3 Table 11 3 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address C...

Page 309: ...occurs at a delayed branch instruction or its delay slot the break may not actually take place until the first instruction at the branch destination 11 3 4 Break on X Y Memory Bus Cycle 1 The break co...

Page 310: ...r can be clearly determined except for when data is included in the break condition If the I bus is specified as a break condition the instruction at which the break should occur cannot be clearly det...

Page 311: ...ch source address and branch destination address are stored in BRSR and BRDR respectively 2 The values stored in BRSR and BRDR are as given below due to the kind of branch If a branch occurs due to a...

Page 312: ...6 Data H 00000000 Data mask H 00000000 Bus cycle L bus instruction fetch before instruction execution read operand size is not included in the condition A user break occurs after an instruction of add...

Page 313: ...on fetch before instruction execution read operand size is not included in the condition On channel A no user break occurs since instruction fetch is not a write cycle On channel B no user break occur...

Page 314: ...n of address H 00000500 is executed On channel B a user break occurs after the instruction of address H 00001000 are executed four times and before the fifth time Example 1 6 Register specifications B...

Page 315: ...ddress H 00123454 word read from address H 00123456 or byte read from address H 00123456 On channel B a user break occurs when word H A512 is written in addresses H 000ABC00 to H 000ABCFE Example 2 2...

Page 316: ...H 00314156 in the memory space On channel B a user break occurs when the I bus writes byte data H 7 in address H 00055555 11 4 Usage Notes 1 The CPU can read from or write to the UBC registers via the...

Page 317: ...hen a post execution break or data access break occurs simultaneously with a completion type exception TRAPA that has higher priority though a break does not occur the condition match flag is set 5 No...

Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...

Page 319: ...synchronous or asynchronous MPX I O burst MPX I O and SDRAM for each address space Can select the data bus width 8 16 or 32 bits for each address space Controls the insertion of the wait state for eac...

Page 320: ...address data multiplexing Supports burst transfer 8 Burst ROM interface clock synchronous Can connect directly to a ROM of the clock synchronous type 9 Bus arbitration Shares all of the resources with...

Page 321: ...roller Legend Module bus BSC CS0 CS2 CS3 CS4 CS5A CS5B CS6A CS6B WAIT MD3 A25 to A0 D31 to D0 BACK BREQ BS RD WR RD WE3 to WE0 RASU RASL CASU CASL CKE DQMxx AH FRAME CMNCR CSnWCR RWTCNT CSnBCR SDCR RT...

Page 322: ...le signal WE3 ICIOWR AH Output Indicates that D31 to D24 are being written to Connected to the byte select signal when a byte selection SRAM is connected Functions as the address hold signal when the...

Page 323: ...12 3 1 Area Division In the architecture of this LSI both logical spaces and physical spaces have 32 bit address spaces The cache access method is shown by the upper three bits For details see sectio...

Page 324: ...20000000 n n 1 to 6 The address range for area 7 is H 1C000000 to H 1FFFFFFF The address space H 1C000000 H 20000000 n H 1FFFFFFF H 20000000 n n 0 to 7 corresponding to the area 7 shadow space is rese...

Page 325: ...ion SRAM SDRAM 64 Mbytes H 0C000000 to H 0FFFFFFF Area 3 Normal memory Byte selection SRAM SDRAM 64 Mbytes H 10000000 to H 13FFFFFF Area 4 Normal memory Byte selection SRAM Burst ROM asynchronous 64 M...

Page 326: ...lection SRAM Burst ROM Asynchronous 64 Mbytes H 14000000 to H 17FFFFFF Area 5 2 Normal memory Byte selection SRAM MPX I O 64 Mbytes H 18000000 to H 1BFFFFFF Area 6 2 Normal memory Byte selection SRAM...

Page 327: ...ction 24 List of Registers Do not access spaces other than CS0 until the termination of the setting the memory interface Common control register CMNCR Bus control register for area 0 CS0BCR Bus contro...

Page 328: ...t Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 WAITSEL 0 R W WAIT Signal Sampling Timing Specification Specifies t...

Page 329: ...t a bus mastership request during DMA burst transfer 10 Accepts neither a refresh request nor a bus mastership request during DMA burst transfer 11 Reserved setting prohibited 8 7 6 DMAIW2 DMAIW1 DMAI...

Page 330: ...e with DACK even when the continuous accesses to an external device with DACK are performed 0 Idle cycles inserted when another device drives the data bus after an external device with DACK drove it 1...

Page 331: ...ter is initialized to H 36DB0600 by a power on reset and it is not initialized by a manual reset and in the standby mode Do not access external memory other than area 0 until CSnBCR register initializ...

Page 332: ...serted 010 2 idle cycles inserted 011 4 idle cycles inserted 100 6 idle cycles inserted 101 8 idle cycles inserted 110 10 idle cycles inserted 111 12 idle cycles inserted 24 23 22 IWRWS2 IWRWS1 IWRWS0...

Page 333: ...dle cycles inserted 100 6 idle cycles inserted 101 8 idle cycles inserted 110 10 idle cycles inserted 111 12 idle cycles inserted 18 17 16 IWRRS2 IWRRS1 IWRRS0 1 1 1 R W R W R W Idle Cycles for Read R...

Page 334: ...cify the type of memory connected to a space 0000 Normal space 0001 Burst ROM clock synchronous 0010 MPX I O 0011 Byte selection SRAM 0100 SDRAM 0101 Reserved Setting prohibited 0110 Burst MPX I O 011...

Page 335: ...dth can be specified as 8 bits or 16 bits by the address according to the SZSEL bit in CS5BWCR by specifying these bits to 11 2 The data bus width for area 0 is specified by the external pin The BSZ1...

Page 336: ...nBCR register first then specify the CSnWCR register CSnWCR is initialized to H 00000500 by a power on reset and it is not initialized by a manual reset and in the standby mode Normal Space Byte Selec...

Page 337: ...0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved Se...

Page 338: ...16 and then set the bits TYPE 2 0 in CS0BCR Reserved bits other than above should not be set to 1 For details on the burst ROM interface see Burst ROM Clock Asynchronous CS2WCR CS3WCR Bit Bit Name In...

Page 339: ...0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved Se...

Page 340: ...rts the RD WR signal during the write access cycle 1 Asserts the WEn signal during the read access cycle and asserts the RD WR signal at the write timing 19 0 R Reserved This bit is always read as 0 T...

Page 341: ...umber of Read Access Wait Cycles Specify the number of cycles that are necessary for read access 0000 No cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8...

Page 342: ...00 0 5 cycles 01 1 5 cycles 10 2 5 cycles 11 3 5 cycles CS5AWCR Bit Bit Name Initial Value R W Description 31 to 19 All 0 R Reserved These bits are always read as 0 The write value should always be 0...

Page 343: ...Number of Read Access Wait Cycles Specify the number of cycles that are necessary for read access 0000 No cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111...

Page 344: ...CS5BWCR Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 SZSEI 0 R W MPX IO Interface Bus Width Specification...

Page 345: ...when the byte selection SRAM interface is used 0 Asserts the WEn signal at the read timing and asserts the RD WR signal during the write access cycle 1 Asserts the WEn signal during the read access c...

Page 346: ...umber of Read Access Wait Cycles Specify the number of cycles that are necessary for read access 0000 No cycle 0001 1 cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8...

Page 347: ...number of delay cycles from RD and WEn negation to address and CSn negation 00 0 5 cycles 01 1 5 cycles 10 2 5 cycles 11 3 5 cycles CS6AWCR Bit Bit Name Initial Value R W Description 31 to 13 All 0 R...

Page 348: ...0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved Se...

Page 349: ...ys be 0 20 BAS 0 R W Byte Selection SRAM Byte Access Selection Specifies the WEn and RD WR signal timing when the byte selection SRAM interface is used 0 Asserts the WEn signal at the read timing and...

Page 350: ...cles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved Setting proh...

Page 351: ...lue should always be 0 20 BEN 0 R W Burst Enable Specification Enables or disables 8 burst access for a 16 bit bus width or 16 burst access for an 8 bit bus width during 16 byte access If this bit is...

Page 352: ...cycles 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 7 W3 W2 W1 W0 1 0 1 0 R W R W R W R W Number of Access Wait Cycles Specify the number of wait...

Page 353: ...s are always read as 0 The write value should always be 0 20 BEN 0 R W Burst Enable Specification Enables or disables 8 burst access for a 16 bit bus width or 16 burst access for an 8 bit bus width du...

Page 354: ...etween the second or later access cycles in burst access 00 No cycle 01 1 cycle 10 2 cycles 11 3 cycles 15 to 13 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12...

Page 355: ...s 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved S...

Page 356: ...1 3 5 cycles SDRAM CS2WCR Bit Bit Name Initial Value R W Description 31 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 1 R Reserved This bit is always rea...

Page 357: ...ing of the ACTV command for the same bank Until entering the power down mode or deep power down mode From issuing of the PALL command to issuing of the REF command in auto refreshing From issuing of t...

Page 358: ...artup wait cycles during the periods shown below From issuing of the WRITA command by this LSI to starting of auto precharge in SDRAM The number of cycles from issuing the WRITA command to issuing the...

Page 359: ...ng of the ACTV REF MRS command The setting for areas 2 and 3 is common 00 2 cycles Initial value 01 3 cycles 10 5 cycles 11 8 cycles Note If both areas 2 and 3 are specified as SDRAM WTRP 1 0 WTRCD 1...

Page 360: ...byte 0 0 1 Word 2 byte 0 1 0 Longword 4 bytes 0 1 1 Reserved quad word 8 bytes 1 0 0 16 bytes 1 0 1 Reserved 32 bytes 1 1 0 Reserved 64 bytes Transfer size when MPXMD 1 D31 D30 D29 Transfer Size 0 0 0...

Page 361: ...cycle 0010 2 cycles 0011 3 cycles 0100 4 cycles 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 11...

Page 362: ...0 R Reserved These bits are always read as 0 The write value should always be 0 17 16 BW1 BW0 0 0 R W R W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the secon...

Page 363: ...s 0101 5 cycles 0110 6 cycles 0111 8 cycles 1000 10 cycles 1001 12 cycles 1010 14 cycles 1011 18 cycles 1100 24 cycles 1101 Reserved Setting prohibited 1110 Reserved Setting prohibited 1111 Reserved S...

Page 364: ...hese bits are always read as 0 The write value should always be 0 20 19 A2ROW1 A2ROW0 0 0 R W R W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2 00 11 bi...

Page 365: ...read at the falling edge of CKIO This mode is suitable for SDRAM with low frequency clock 0 Command address and write data for SDRAM is output at the rising edge of CKIO Read data from SDRAM is latch...

Page 366: ...ss to the external memory other than the SDRAM or to the internal I O resister 8 BACTV 0 R W Bank Active Mode Specifies to access whether in auto precharge mode using READA and WRITA commands or in ba...

Page 367: ...and in the standby mode When the RTCSR is written the upper 16 bits of the write data must be H A55A to cancel write protection The clock which counts up the refresh timer counter RTCNT is adjusted it...

Page 368: ...counting up 001 B 4 010 B 16 011 B 64 100 B 256 101 B 1024 110 B 2048 111 B 4096 2 1 0 RRC2 RRC1 RRC0 0 0 0 R W R W R W Refresh Count Specify the number of continuous refresh cycles when the refresh...

Page 369: ...e bits are always read as 0 7 to 0 All 0 R W 8 Bit Counter 12 4 7 Refresh Time Constant Register RTCOR RTCOR is an 8 bit register When RTCOR matches RTCNT the CMF bit in RTCSR is set to 1 and RTCNT is...

Page 370: ...This counter is provided to minimize the time from releasing a reset for flash memory to the first access If a value is written to the lower seven bits of this register the counter starts to incremen...

Page 371: ...from a byte width device the read operation must be done four times In this LSI data alignment and conversion of data length is performed automatically between the respective interfaces Table 12 5 th...

Page 372: ...E3 DQMUU WE2 DQMUL WE1 DQMLU WE0 DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert Word access at 0...

Page 373: ...e access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert 1st time at 0 Data 15 to 8 Assert Word access at 0 2nd time...

Page 374: ...completed in two cycles The BS signal is asserted for one cycle to indicate the start of a bus cycle CKIO Note The waveform for DACKn is when active low is specified A25 to A0 RD WR RD WR D31 to D0 DA...

Page 375: ...2 4 and 12 5 show the basic timings of normal space accesses If the WM bit in CSnWCR is cleared to 0 a Tnop cycle is inserted after the CSn space access to evaluate the external wait figure 12 4 If th...

Page 376: ...3 0400 CKIO A25 to A0 RD WR D15 to D0 DACKn CSn T1 T2 T1 T2 RD WEn BS WAIT D15 to D0 Read Write Note The waveform for DACKn is when active low is specified Figure 12 5 Continuous Access for Normal Spa...

Page 377: ...f 982 REJ09B0023 0400 A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O...

Page 378: ...0 CS OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 12 7 Example of 16 Bit Data Width SRAM Connection This LSI 128k 8 bit SRAM A16 A0 CS O...

Page 379: ...ert wait cycles independently in read access and in write access The areas other than 4 5A and 5B have common access wait for read cycle and write cycle The specified number of Tw cycles are inserted...

Page 380: ...e wait is specified as a software wait The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw cycle to the T2 cycle T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31...

Page 381: ...a flexible interface to an external device can be obtained Figure 12 11 shows an example A Th cycle and a Tf cycle are added before and after an ordinary cycle respectively In these cycles RD and WEn...

Page 382: ...from cycle Ta2 to cycle Ta3 Because cycle Ta1 has a high impedance state collisions of addresses and data can be avoided without inserting idle cycles even in continuous accesses Address output is inc...

Page 383: ...T1 CKIO A25 to A16 CSn RD WR RD D7 to D0 or D15 to D0 WEn D7 to D0 or D15 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note The waveform for DACKn is when active low is s...

Page 384: ...CS5B RD WR RD D7 to D0 or D15 to D0 WEn D7 to D0 or D15 to D0 BS Read Write T2 DACKn Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note The waveform for DACKn is when active low is specif...

Page 385: ...to 2 spaces The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits Burst read single write burst length 1 and burst read burst write burst length 1 are supported as the...

Page 386: ...gned to the same CS space 4 banks specified by RASL and CASL and 4 banks specified by RAS and CAS When accessing the address with A25 0 RASL and CASL are asserted When accessing the address with A25 1...

Page 387: ...82 REJ09B0023 0400 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD WR D15 D0 DQMLU DQMLL 64M SDRAM 1M 16 bit 4 bank A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML This LSI Unused Unused Figure 12 16 Exa...

Page 388: ...00 A14 A1 CKE CKIO CSn RASU CASU RASL CASL RD WR D15 D16 DQMLU DQMLL 64M SDRAM 1M 16 bit 4 bank A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML A13 A0 CKE CLK CS RAS CAS WE I O15 I O0 DQMU DQML This...

Page 389: ...pins Do not specify those bits in the manner other than this table otherwise the operation of this LSI is not guaranteed A25 to A18 are not multiplexed and the original values of address are always o...

Page 390: ...ed A14 A22 2 A22 2 A12 BA1 A13 A21 2 A21 2 A11 BA0 Specifies bank A12 A20 2 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A...

Page 391: ...2 Unused A14 A22 2 A22 2 A13 BA1 A13 A21 A13 A12 BA0 Specifies bank A12 A20 2 L H 1 A10 AP Specifies address precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A...

Page 392: ...13 A22 A13 A11 Address A12 A21 L H 1 A10 AP Specifies address precharge A11 A20 2 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A1...

Page 393: ...3 A23 A13 A11 Address A12 A22 L H 1 A10 AP Specifies address precharge A11 A21 A11 A9 A10 A20 2 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12...

Page 394: ...A13 A22 A13 A11 Address A12 A21 L H 1 A10 AP Specifies address precharge A11 A20 2 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2...

Page 395: ...25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 Unused A13 A21 2 A21 2 A12 BA1 A12 A20 2 A20 2 A11 BA0 Specifies bank A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8...

Page 396: ...17 A16 A24 A16 A15 A23 A15 Unused A14 A22 2 A22 2 A13 BA1 A13 A21 2 A21 2 A12 BA0 A12 A20 A20 A11 Specifies bank Address A11 A19 L H 1 A10 AP Specifies address precharge A10 A18 A10 A9 A9 A17 A9 A8 A8...

Page 397: ...A16 A25 A16 A15 A24 A15 Unused A14 A23 A23 2 A13 BA1 A13 A22 2 A22 2 A12 BA0 Specifies bank A12 A21 2 A12 A11 Address A11 A20 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A...

Page 398: ...A16 A26 A16 A15 A25 A15 Unused A14 A24 2 A24 2 A13 BA1 A13 A23 2 A23 2 A12 BA0 Specifies bank A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A1...

Page 399: ...A23 2 A13 BA0 Specifies bank A13 A22 A13 A12 A12 A21 A12 A11 Address A11 A20 2 L H 1 A10 AP Specifies address precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4...

Page 400: ...A24 2 A13 BA0 Specifies bank A13 A23 A13 A12 A12 A22 A12 A11 Address A11 A21 L H 1 A10 AP Specifies address precharge A10 A20 2 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4...

Page 401: ...command is issued in the Tc1 Tc2 and Tc3 cycles the READA command is issued in the Tc4 cycle and the read data is received at the rising edge of the external clock CKIO in the Td1 to Td4 cycles The T...

Page 402: ...y The CAS latency for the SDRAM is normally defined as up to three cycles However the CAS latency in this LSI can be specified as 1 to 4 cycles This CAS latency can be achieved by connecting a latch c...

Page 403: ...Td2 Td3 Td1 Trw Tw CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low...

Page 404: ...burst length is set to 1 in synchronous DRAM burst read single write mode only the required data is output Figure 12 20 shows the single read basic timing Tap Tr Tc1 Tde Td1 CKIO A25 to A0 CSn RD WR...

Page 405: ...ommand is output in the Tr cycle the WRIT command is issued in the Tc1 Tc2 and Tc3 cycles and the WRITA command is issued to execute an auto precharge in the Tc4 cycle In the write cycle the write dat...

Page 406: ...400 Tc4 Tap Tr Tc2 Tc3 Tc1 Trwl CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is wh...

Page 407: ...n and the data bus width is larger than or equal to access size Figure 12 22 shows the single write basic timing Tap Tr Tc1 Trwl CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1...

Page 408: ...CTV command is determined by the WTRP1 and WTPR0 bits in CS3WCR In a write when an auto precharge is performed a command cannot be issued to the same bank for a period of Trwl Tap cycles after issuanc...

Page 409: ...If there is an access to a different row address in the bank active state after this is detected the bus cycle in figure 12 24 or 12 27 is executed instead of that in figure 12 25 or 12 28 In bank ac...

Page 410: ...Td4 Tde Td2 Td3 Td1 CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active l...

Page 411: ...4 Td2 Td3 Td1 Tde Tr CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active l...

Page 412: ...J09B0023 0400 Tr Tc1 CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active l...

Page 413: ...0 Tnop Tc1 CKIO A25 to A0 CSn RD WR RASL RASU DQMxx D31 to D0 BS DACKn 2 A12 A11 1 CASL CASU Notes 1 Address pin to be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is spec...

Page 414: ...Timing Bank Active Different Row Addresses in the Same Bank Refreshing This LSI has a function for controlling synchronous DRAM refreshing Auto refreshing can be performed by clearing the RMODE bit t...

Page 415: ...generated and an auto refresh is performed for the number of times specified by the RRC2 to RRC0 At the same time RTCNT is cleared to zero and the count up is restarted Figure 12 29 shows the auto ref...

Page 416: ...nerated within the synchronous DRAM Self refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1 After starting the self refreshing PALL command is issued in Tp cycle after...

Page 417: ...setting the initial value of RTCNT Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately After self refreshing has been set the self refresh state continu...

Page 418: ...the bus will not be released until the refresh is completed Low Frequency Mode When the SLOW bit in SDCR is set to 1 output of commands addresses and write data and fetch of read data are performed at...

Page 419: ...2 31 Low Frequency Mode Access Timing Power Down Mode If the PDOWN bit in the SDCR register is set to 1 the SDRAM is placed in the power down mode by bringing the CKE signal to the low level in the no...

Page 420: ...be connected to pin A10 of SDRAM 2 The waveform for DACKn is when active low is specified Figure 12 32 Power Down Mode Access Timing The conditions to shift to the power down mode are as follows Writ...

Page 421: ...RAM and to address H A4FD5000 X for area 3 synchronous DRAM In this operation the data is ignored but the mode write is performed as a byte size access To set burst read single write CAS latency 2 to...

Page 422: ...sh command is then issued 8 times An MRS command mode register write command is finally issued Idle cycles of which number is specified by the WTRP1 and WTRP0 bits in CS3WCR are inserted between the P...

Page 423: ...n and that power consumption is low during refresh under user conditions such as the operating temperature The partial refresh is effective in systems in which there is data in a work area other than...

Page 424: ...efresh H A4FD5XX0 H 0YYYYYYY 32 bits H 0000XX0 H YYYYYYY CS2 MRS EMRS without refresh H A4FD4XX0 H 1YYYYYYY 32 bits H 0000XX0 H YYYYYYY CS3 MRS EMRS without refresh H A4FD5XX0 H 1YYYYYYY 32 bits H 000...

Page 425: ...as If the RMODE bit in the SDCR is set to 1 while the DEEP and RFSH bits in the SDCR are set to 1 the low power SDRAM enters the deep power down mode If the RMODE bit is cleared to 0 the CKE signal is...

Page 426: ...the number of wait cycles specified by the W1 to W0 bits in the CSnWCR register is inserted In the access to the burst ROM clock asynchronous the BS signal is asserted only to the first access cycle A...

Page 427: ...tial value the write access timing of the byte selection SRAM interface is the same as that for the normal space interface While in read access of a byte selection SRAM interface the byte selection si...

Page 428: ...14 2005 Page 378 of 982 REJ09B0023 0400 CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified T1 T2 High Figure 1...

Page 429: ...14 2005 Page 379 of 982 REJ09B0023 0400 T1 T2 High CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified Figure 1...

Page 430: ...of 982 REJ09B0023 0400 T2 Th Th T1 Tw High CKIO A25 to A0 CSn WEn RD WR RD RD D31 to D0 D31 to D0 RD WR BS DACKn Read Write Note The waveform for DACKn is when active low is specified Figure 12 39 Byt...

Page 431: ...D31 D16 WE3 WE2 D15 D0 WE1 WE0 This LSI A15 A0 CS OE WE I O15 I O0 UB LB 64k 16 bit SRAM Figure 12 40 Example of Connection with 32 Bit Data Width Byte Selection SRAM This LSI A16 A1 CSn RD RD WR D15...

Page 432: ...dress and the access size for the MPX I O interface are output to D25 to D0 and D31 to D29 respectively in address cycles For the access sizes of D31 to D29 see the description of the CS6BWCR register...

Page 433: ...005 Page 383 of 982 REJ09B0023 0400 Tm1 Tmd1w Tmd1 A D Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6B RD WR WAIT BS DACKn Figure 12 43 Burst MPX Space...

Page 434: ...ge 384 of 982 REJ09B0023 0400 Tm1 Tmd1w Tmd1w Tmd1 A D Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6B RD WR WAIT BS DACKn Figure 12 44 Burst MPX Space...

Page 435: ...REJ09B0023 0400 Tm1 Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 A D0 D1 D2 D3 Note The waveform for DACKn is when active low is specified CKIO D31 to D0 A25 to A0 FRAME CS6B RD WR WAIT BS DACKn Figure 12 45 Burst MPX S...

Page 436: ...the same way as a normal space This interface is valid only for area 0 In the first access cycle wait cycles are inserted In this case the number of wait cycles to be inserted is specified by the W3...

Page 437: ...gth 8 Wait Cycles Inserted in First Access 2 Wait Cycles Inserted in Second and Subsequent Accesses 1 12 5 11 Wait between Access Cycles As the operating frequency of LSIs becomes higher the off opera...

Page 438: ...the external bus for accessing different memory For accessing different memory insert idle cycles as follows The byte selection SRAM interface with the BAS bit 1 specified is handled as an SDRAM inte...

Page 439: ...3 3 4 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 3 3 4 5 1 1 1 1 0 1 1 1 1 2 1 1 2 3 3 3 4 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 3 3 4 5 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 5 2 2 2 2 2 2 2 2 2 2 2 2...

Page 440: ...Read to Write 2 Continuous Write 1 Write to Read 2 1 0 2 0 0 2 0 0 0 0 2 1 1 2 1 1 1 1 2 1 1 2 1 1 0 1 2 1 1 2 1 1 1 2 2 2 2 2 2 2 0 2 2 2 2 2 2 2 1 4 4 4 4 4 4 4 0 4 4 4 4 4 4 4 0 1 n n 6 n n n n n...

Page 441: ...e from the External Device with DACK 1 Transfer from the external device with DACK to the normal space interface BSC Register Setting 3 When Access Size is Less than Bus Width CSnWCR WM Setting CMNCR...

Page 442: ...ffected by changing a clock ratio 1 Minimum number of idle cycles between the upper and lower 16 bit access cycles in the 32 bit access cycle when the bus width is 16 bits and the minimum number of id...

Page 443: ...3 3 3 3 3 3 4 5 3 3 3 3 2 3 0 1 3 2 2 2 2 4 4 4 4 3 3 4 5 4 4 4 4 2 4 0 2 0 3 3 3 3 2 2 2 3 3 3 4 5 2 2 2 2 3 2 0 2 1 3 3 3 3 3 3 3 3 3 3 4 5 3 3 3 3 3 3 0 2 2 3 3 3 3 4 4 4 4 3 3 4 5 4 4 4 4 3 4 0 2...

Page 444: ...3 3 3 3 2 1 0 3 3 3 3 2 2 2 2 3 3 4 5 2 2 2 2 3 2 2 1 1 3 3 3 3 2 2 2 2 3 3 4 5 2 2 2 2 3 2 2 1 2 3 3 3 3 3 3 3 3 3 3 4 5 3 3 3 3 3 3 2 1 3 3 3 3 3 4 4 4 4 3 3 4 5 4 4 4 4 3 4 2 2 0 3 3 3 3 2 2 2 3 3...

Page 445: ...5 4 4 4 4 5 5 5 5 4 4 4 4 5 4 4 2 2 5 5 5 5 4 4 4 4 5 5 5 5 4 4 4 4 5 4 4 2 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4 3 0 5 5 5 5 4 4 4 4 5 5 5 5 4 4 4 4 5 4 4 3 1 5 5 5 5 4 4 4 4 5 5 5 5 4 4 4 4 5 4 4...

Page 446: ...sfer from the external device with DACK to the SDRAM interface BSC Register Setting 2 CMNCR DMAIW Setting CS3WCR WTRP Setting CS3WCR TRWL Setting Minimum Number of Idle Cycles 0 0 0 3 0 0 1 3 0 0 2 3...

Page 447: ...R WTRP Setting CS3WCR TRWL Setting Minimum Number of Idle Cycles 1 3 2 5 1 3 3 6 2 0 1 3 2 0 2 3 2 0 3 3 2 1 0 3 2 1 1 3 2 1 2 3 2 1 3 4 2 2 0 3 2 2 1 3 2 2 2 4 2 2 3 5 2 3 0 3 2 3 1 4 2 3 2 5 2 3 3 6...

Page 448: ...4 2 0 3 2 1 3 2 2 3 2 3 4 4 0 5 4 1 5 4 2 5 4 3 5 n n 6 n 1 Notes DMAC is operated by B The minimum number of idle cycles is not affected by changing a clock ratio 1 For single transfer from the exter...

Page 449: ...ple between bus cycles when longword access is made to a memory with a data bus width of 8 bits 5 16 byte transfer by the DMAC 6 Setting the BLOCK bit in the CMNCR register to 1 The LSI has the bus ma...

Page 450: ...not be executed until the LSI obtains the bus mastership The BREQ input signal is ignored in the standby mode and the BACK output signal are placed in the high impedance state If the bus mastership re...

Page 451: ...the first access To ensure this minimum time the bus state controller supports a 7 bit counter RWTCNT At power on reset the RWTCNT is cleared to 0 After power on reset RWTCNT is counted up synchronous...

Page 452: ...nding to the cache the cache is modified In this case data to be modified is first saved to the internal buffer 16 byte data including the data corresponding to the address is then read and data in th...

Page 453: ...ted If BSC registers are modified while the write buffer is functioning correct access cannot be performed Thus do not modify BSC registers immediately after the writing has finished If BSC registers...

Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...

Page 455: ...bytes longword 4 Maximum transfer count 16 777 216 transfers 24 bits Address mode Dual address mode and single address mode are supported Transfer requests External request On chip peripheral module...

Page 456: ...troller DREQ0 DREQ1 DEIn DACK0 DACK1 TEND External RAM Bus interface Bus state controller External device memory mapped External device with acknowledge ment Request priority control Start up control...

Page 457: ...on Channel Name Symbol I O Function DMA transfer request DREQ0 I DMA transfer request input from external device to channel 0 DMA transfer request acknowledge DACK0 O Strobe output to an external I O...

Page 458: ...ol register_0 CHCR_0 Channel 1 DMA source address register_1 SAR_1 DMA destination address register_1 DAR_1 DMA transfer count register_1 DMATCR_1 DMA channel control register _1 CHCR_1 Channel 2 DMA...

Page 459: ...functions and during a DMA transfer these registers indicate the next destination address When the data of an external device with DACK is transferred in the single address mode the DAR is ignored To...

Page 460: ...T1 at an On chip peripheral module request Other than this please specify 0 to be this bit then 0 It transmits once by one transfer request 1 It transmits the number of setting times of DMATCR by one...

Page 461: ...nowledge Level AL specifies the DACK acknowledge signal output is high active or low active This bit is valid only in CHCR_0 and CHCR_1 This bit is always read as 0 in CHCR_2 and CHCR_3 The write valu...

Page 462: ...ill be sent to the DMAC The changing of transfer request source should be done in the state that DMA enable bit DE is set to 0 0 0 0 0 External request dual address mode 0 0 0 1 Reserved Setting prohi...

Page 463: ...nored 00 DREQ detected in low level 01 DREQ detected at falling edge 10 DREQ detected in high level 11 DREQ detected at rising edge 5 TB 0 R W Transfer Bus Mode This bit specifies the bus mode when DM...

Page 464: ...request is generated 1 TE 0 R W Transfer End Flag This bit shows that DMA transfer ends TE is set to 1 when data transfer ends when DMATCR becomes to 0 The TE bit is not set to 1 in the following cas...

Page 465: ...o 1 In this time all of the bits TE NMIF in DMAOR and AE must be 0 s In an external request or peripheral module request DMA transfer starts if DMA transfer request is generated by the devices or peri...

Page 466: ...on 31 30 All 0 R Reserved These bits are always read as 0 The write value should always be 0 29 28 CMS1 CMS0 0 0 R W R W Cycle Steal Mode Select 1 0 These bits select either normal mode or intermitten...

Page 467: ...indicates that an address error occurred during DMA transfer If this bit is set during data transfer transfers on all channels are suspended The CPU cannot write 1 to this bit This bit can only be cle...

Page 468: ...ways be 0 5 4 3 2 RC0 RC1 RC2 RC3 0 0 0 0 R W R W R W R W Round Robin Cannel Select RC3 RC2 RC1 and RC0 select the priority level between channels when there are transfer requests for multiple channel...

Page 469: ...priority mode bit is modified after a DMA transfer the channel priority is initialized to be changed If fixed mode 2 is specified the channel priority is specified as CH0 CH2 CH3 CH1 If fixed mode 1...

Page 470: ...H2 1 0 CH0 CH1 CH3 CH2 0 1 1 1 CH1 1 0 CH0 CH2 CH3 CH1 1 0 1 1 1 CH2 1 0 CH0 CH3 CH1 CH2 2 1 1 0 0 CH0 1 0 CH1 CH0 CH2 CH3 1 1 1 0 CH0 1 0 CH1 CH2 CH0 CH3 3 1 1 1 0 CH1 1 0 CH2 CH0 CH1 CH3 1 1 1 1 CH0...

Page 471: ...register is initialized to H 0000 by power on manual reset The previous value is held in standby mode or module standby mode DMARS0 Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 C1MID5...

Page 472: ...R W R W R W R W R W Transfer request module ID for DMA channel 3 MID See table 13 3 9 8 C3RID1 C3RID0 0 0 R W R W Transfer request module ID for DMA channel 3 RID See table 13 3 7 6 5 4 3 2 C2MID5 C2...

Page 473: ...10000 B 00 Transmit H 41 B 01 Receive MTU0 H A8 B 101010 B 00 TGI0A MTU1 H C0 B 110000 B 00 TGI1A MTU2 H C8 B 110010 B 00 TGI2A MTU3 H D0 B 110100 B 00 TGI3A MTU4 H E8 B 111010 B 00 TGI4A USB H A0 B 1...

Page 474: ...l registers CHCR DMA operation register DMAOR and DMA extension resource selector DMARS are set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1...

Page 475: ...MATCR SAR and DAR updated DEI interrupt request when IE 1 TE 1 No Yes No Yes No Yes Yes No Yes No 3 2 Start Transfer aborted DMATCR 0 Transfer request occurs 1 DE DME 1 and NMIF AE TE 0 NMIF 1 or AE 1...

Page 476: ...hen the DE bits of CHCR_0 to CHCR_3 and the DME bit of the DMAOR are set to 1 the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and the NMIF bit of DMAOR are all 0 External Request Mode I...

Page 477: ...ing acknowledge signal DACK for the accepted DREQ the DREQ pin again becomes request accept enabled state When DREQ is used by level detection there are following two cases by the timing to detect the...

Page 478: ...set the transfer destination as the corresponding SCIF receive data register Requests from the USB are handled in an analogous way If a transfer is requested from the A D converter 0 and A D converter...

Page 479: ...rst cycle steal 101000 00 USB transmitter EP2FIFO empty transfer request Any USBEPDR2 Cycle steal 01 USB receiver EP1FIFO full transfer request USBEPDR1 Any Cycle steal 101100 00 A D converter 1 ADI A...

Page 480: ...CH1 CH2 CH3 CH3 CH0 CH1 CH2 CH0 CH1 CH2 CH3 1 When channel 0 transfers Initial priority order Initial priority order Initial priority order Priority order afrer transfer Priority order afrer transfer...

Page 481: ...ds channel 0 becomes lowest priority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends cha...

Page 482: ...le 13 8 Table 13 8 Supported DMA Transfers Destination Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module X Y Memory U Memory External device with...

Page 483: ...ata is written to the other external memory in a write cycle Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source modu...

Page 484: ...emory Destination Ordinary Memory 2 Single Address Mode In single address mode either the transfer source or transfer destination peripheral device is accessed selected by means of the DACK signal and...

Page 485: ...y External device with DACK Data flow Figure 13 7 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode 1 transfer between an external device with DACK and a memor...

Page 486: ...ternal device with DACK CK A25 to A0 D31 to D0 DACKn CSn WE CK A25 to A0 D31 to D0 DACKn CSn RD Figure 13 8 Example of DMA Transfer Timing in Single Address Mode Bus Modes There are two bus modes cycl...

Page 487: ...omplete If the next transfer request occurs after that DMAC gets the bus mastership from other bus master after waiting for 16 or 64 clocks in B count DMAC then transfers data of one unit and returns...

Page 488: ...however when the DREQ pin is driven high the bus passes to the other bus master after the DMAC transfer request that has already been accepted ends even if the transfer end conditions have not been s...

Page 489: ...y U memory and memory mapped external device All 1 B C 8 16 32 128 0 to 3 5 X Y memory U memory and on chip peripheral module All 2 B C 3 8 16 32 128 4 0 to 3 5 Dual X Y memory U memory and external m...

Page 490: ...e burst mode data transfer on the channel that has the highest priority is given precedence When DMA transfer is being performed on multiple channels bus mastership is not released to another bus mast...

Page 491: ...CKIO Bus cycle Bus cycle DREQ Rising DACK Active high DREQ Overrun 1 at high level DACK Active high CPU CPU CPU DMAC CKIO CPU CPU CPU DMAC 1st acceptance 2nd acceptance 1st acceptance 2nd acceptance A...

Page 492: ...REQ Rising DACK Active high Bus cycle DREQ Overrun 1 at high level DACK Active high Non sensitive period Non sensitive period 2nd acceptance 2nd acceptance 3rd acceptance Figure 13 16 Example of DREQ...

Page 493: ...ts are divided for data alignment as shown in figure 13 18 CKIO Address DACKn TENDn WAIT CSn T1 T2 Taw T1 T2 Active low Active low Note TEND is asserted for the last transfer unit of DMA transfers If...

Page 494: ...ansfers as for transfers with other transfer units B Completion of transfer indicated by DE 0 in CHCR Clearing of the DMA enable bit DE of CHCR halts DMA transfer on the corresponding channel In this...

Page 495: ...request by software in the same way as when an address error occurs during a read cycle described above B Completion of transfer by clearing DME of DMAOR to 0 When the DME bit of DMAOR is cleared to 0...

Page 496: ...s executed by the DMAC If the transfer restart is not desired prevent the transfer from restarting by implementing one of the measures shown below Preventive measures Clear the DE bit of CHCR in the e...

Page 497: ...DREQ pin in the above access are shown in figures 13 19 to 13 22 CKIO CPU DMAC write or read Bus cycle Non sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible Non sensitive period...

Page 498: ...e possible Non sensitive period CPU DMAC write Non sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible Non sensitive period CKIO Bus cycle DREQ Overrun 0 high level DACK High active...

Page 499: ...us cycle Figure 13 22 Example of DREQ Input Detection in Cycle Steal Mode Level Detection When DACK is Divided to 2 by Idle Cycles 3 Notes For the external access described in 2 above note the followi...

Page 500: ...Section 13 Direct Memory Access Controller DMAC Rev 4 00 Sep 14 2005 Page 450 of 982 REJ09B0023 0400...

Page 501: ...The U memory is divided into page 0 and page 1 according to the addresses The U memory can be accessed from the L bus and I bus In the event of simultaneous accesses to the same address from differen...

Page 502: ...00 H 05000000 H 0501FFFF H 055F0000 H 0560FFFF H 05610000 H 07FFFFFF U memory page1 64 kbytes U memory page0 64 kbytes H 0560FFFF H 05600000 H 055FFFFF H 055F0000 Figure 14 1 U Memory Address Mapping...

Page 503: ...med from space P2 non cacheable space Operation during access from space P0 cannot be guaranteed When the cache is off spaces P0 and P2 can both be used 14 6 Sleep Mode In sleep mode the U memory cann...

Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...

Page 505: ...the AUD 15 1 Features The user debugging interface H UDI is a serial I O interface which conforms to JTAG Joint Test Action Group IEEE Standard 1149 1 and IEEE Standard Test Access Port and Boundary S...

Page 506: ...ed on regardless of using the H UDI function This is different from the JTAG standard See section 15 4 2 Reset Configuration for more information TDI Input Serial data input pin Data transfer to the H...

Page 507: ...initialized to 0 if the TAP is in Capture DR state 15 3 2 Instruction Register SDIR SDIR is a 16 bit read only register The register is in JTAG IDCODE in its initial state It is initialized by TRST a...

Page 508: ...1 1 1 H UDI reset assert 1 0 1 H UDI interrupt 1 1 1 0 JTAG IDCODE Initial value 1 1 1 1 JTAG BYPASS Other than the above Reserved 15 3 3 Boundary Scan Register SDBSR SDBSR is a 469 bit shift registe...

Page 509: ...74 CS2 PTA2 IN 444 IRQ7 PTJ7 IN 473 UCLK PTB0 IN 443 SCK0 PTH0 IN 472 VBUS PTB1 IN 442 D7 OUT 471 SUSPND PTB2 IN 441 D6 OUT 470 XVDATA PTB3 IN 440 D5 OUT 469 TXENL PTB4 IN 439 D4 OUT 468 TXDMNS PTB5 I...

Page 510: ...l 412 AUDATA2 PTJ10 OUT 380 A19 PTA8 Control 411 AUDATA3 PTJ11 OUT 379 A20 PTA9 Control 410 AUDSYNC PTJ12 OUT 378 A21 PTA10 Control 409 IRQ0 PTJ0 OUT 377 A22 PTA11 Control 408 IRQ1 PTJ1 OUT 376 A23 PT...

Page 511: ...PTH10 IN 317 PTF3 IN 348 CTS2 PTH11 IN 316 PTF4 IN 347 TxD2 PTH12 IN 315 PTF5 IN 346 RxD2 PTH13 IN 314 PTF6 IN 345 RTS2 PTH14 IN 313 PTF7 IN 344 TIOC4D PTE0 IN 312 PTG8 IN 343 TIOC4C PTE1 IN 311 PTG9...

Page 512: ...283 TIOC2A PTE9 OUT 251 RTS0 PTH4 Control 282 TIOC1B PTE10 OUT 250 SCK1 PTH5 Control 281 TIOC1A PTE11 OUT 249 CTS1 PTH6 Control 280 TIOC0D PTE12 OUT 248 TxD1 PTH7 Control 279 TIOC0C PTE13 OUT 247 RxD...

Page 513: ...PTF10 Control 190 BREQ PTC6 IN 221 TCLKA PTF11 Control 189 BACK PTC7 IN 220 POE0 PTF12 Control 188 VccQ IN 219 POE1 PTF13 Control 187 VccQ IN 218 POE2 PTF14 Control 186 ASEBRKAK PTC13 IN 217 POE3 PTF...

Page 514: ...S6A PTC3 OUT 125 FRAME PTC5 Control 156 CS5B PTC2 OUT 124 RD Control 155 CS5A PTC1 OUT 123 DACK0 PTC11 Control 154 CS4 PTC0 OUT 122 DACK1 PTC12 Control 153 CS0 OUT 121 D31 PTD15 Control 152 BS OUT 120...

Page 515: ...3 D9 IN 61 A7 OUT 92 D8 IN 60 A6 OUT 91 D25 PTD9 OUT 59 A5 OUT 90 D24 PTD8 OUT 58 A4 OUT 89 D23 PTD7 OUT 57 A3 OUT 88 D22 PTD6 OUT 56 A2 OUT 87 D21 PTD5 OUT 55 A1 OUT 86 D20 PTD4 OUT 54 A0 PTA0 OUT 85...

Page 516: ...A7 Control 9 A1 Control 29 WE2 DQMUL Control 8 A0 PTA0 Control 28 CKE PTA1 Control 7 D15 Control 27 CASL PTA4 Control 6 D14 Control 26 RASL PTA6 Control 5 D13 Control 25 A17 Control 4 D12 Control 24 A...

Page 517: ...read by CPU The IDCODE command is set from the H UDI pin This register can be read from the TDO when the TAP state is Shift DR Writing is disabled Bit Bit Name Initial Value R W Description 31 to 0 DI...

Page 518: ...0 0 1 0 1 1 1 0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR scan 0 0 1 0 0 1 0 1 1 1 0 0 Figure 15 2 TAP Controller State Transitions Note The transition condition is the TMS va...

Page 519: ...iven low while the RESETP pin is negated In this state the CPU does not start up When TRST is driven high H UDI operation is enabled but the CPU does not start up The reset hold state is cancelled by...

Page 520: ...me between the H UDI reset assert command and H UDI reset negate command is the same as time for keeping the RESETP pin low to apply a power on reset H UDI reset assert H UDI reset negate SDIR Chip in...

Page 521: ...n this instruction is executing this LSI s input pin signals are transmitted directly to the internal circuitry and internal circuit values are directly output externally from the output pins This LSI...

Page 522: ...t state the IDCODE mode is entered CLAMP HIGHZ A command can be set in SDIR by the H UDI pins to place the H UDI pins in the CLAMP or HIGHZ mode stipulated by JTAG 15 5 2 Points for Attention 1 Bounda...

Page 523: ...her the continuous transmission reception can be performed I2 C bus format Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automa...

Page 524: ...tput control Transmission reception control circuit ICCR2 ICMR ICSR ICIER ICDRR ICDRS ICDRT I2C bus control register 1 I2C bus control register 2 I2C bus mode register I2C bus status register I2C bus...

Page 525: ...out SDA Note The I2C bus power supply and this LSI s power supply VccQ must be switched ON or OFF simultaneously Figure 16 2 External Circuit Connections of I O Pins 16 2 Input Output Pins Table 16 1...

Page 526: ...I2 C Bus Control Register 1 ICCR1 ICCR1 is an 8 bit readable writable register that enables or disables the I2 C bus interface 2 controls transmission or reception and selects master or slave mode tra...

Page 527: ...address set to SAR and the eighth bit is set to 1 TRS is automatically set to 1 If an overrun error occurs in master receive mode with the clocked synchronous serial format MST is cleared and the mod...

Page 528: ...2 5 kHz 125 kHz 206kHz 375kHz 413kHz 1 100 50 0 kHz 100 kHz 165kHz 300kHz 330kHz 1 0 112 44 6 kHz 89 3 kHz 147kHz 268kHz 295kHz 1 128 39 1 kHz 78 1 kHz 129kHz 234kHz 258kHz 1 0 0 0 56 89 3 kHz 179 kHz...

Page 529: ...0 when the SDA level changes from low to high under the condition of SCL high assuming that the stop condition has been issued Write 1 to BBSY and 0 to SCP to issue a start condition Follow this proce...

Page 530: ...Part Reset This bit resets the control part except for I 2 C registers If this bit is set to 1 when hang up occurs because of communication failure during I 2 C operation I 2 C control part can be re...

Page 531: ...number of transfer bits is indicated With the I 2 C bus format the data is transferred with one addition acknowledge bit should be made between transfer frames If bits BC2 to BC0 are set to a value ot...

Page 532: ...transmit end interrupt TEI at the rising of the ninth clock while the TDRE bit in ICSR is 1 TEI can be canceled by clearing the TEND bit or the TEIE bit to 0 0 Transmit end interrupt request TEI is di...

Page 533: ...dgment Select 0 The value of the receive acknowledge bit is ignored and continuous transfer is performed 1 If the receive acknowledge bit is 1 continuous transfer is halted 1 ACKBR 0 R Receive Acknowl...

Page 534: ...issued When slave mode is changed from receive mode to transmit mode Clearing conditions When 0 is written in TDRE after reading TDRE 1 When data is written to ICDRT 6 TEND 0 R W Transmit End Setting...

Page 535: ...ation Lost Flag Overrun Error Flag This flag indicates that arbitration was lost in master mode with the I 2 C bus format and that the final bit has been received while RDRF 1 with the clocked synchro...

Page 536: ...the general call address is detected in slave receive mode Clearing condition When 0 is written in ADZ after reading ADZ 1 16 3 6 Slave Address Register SAR SAR is an 8 bit readable writable register...

Page 537: ...erefore the CPU cannot write to this register 16 3 9 I2 C Bus Shift Register ICDRS ICDRS is a register that is used to transfer receive data In transmission data is transferred from ICDRT to ICDRS and...

Page 538: ...st frame following a start condition always consists of eight bits S SLA R W A DATA A A A P 1 1 1 1 n 7 1 m a I2C bus format FS 0 b I2C bus format Start condition retransmission FS 0 n Transfer bit co...

Page 539: ...hen write 1 to BBSY and 0 to SCP Start condition issued This generates the start condition 3 After confirming that TDRE in ICSR has been set write the transmit data the first byte data show the slave...

Page 540: ...essing 1 Bit 7 Slave address Address R W Data 1 Data 1 Data 2 Address R W Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 1 2 3 4 5 6 7 8 9 A R W Figure 16 5 Master Transmit Mode Operation Tim...

Page 541: ...ecified by ACKBT in ICIER to SDA at the ninth receive clock pulse 3 After the reception of first frame data is completed the RDRF bit in ICST is set to 1 at the rise of ninth receive clock pulse At th...

Page 542: ...fter clearing TEND and TRS 2 Read ICDRR dummy read 3 Read ICDRR 1 A 2 1 3 4 5 6 7 8 9 9 A TRS RDRF SCL Master output SDA Master output SDA Slave output Bit 7 Master transmit mode Master receive mode B...

Page 543: ...ion procedure and operations in slave transmit mode are described below 1 Set the ICE bit in ICCR1 to 1 Set bits CKS3 to CKS0 in ICCR1 to 1 Initial setting Set the MST and TRS bits in ICCR1 to select...

Page 544: ...CDRT SCL Master output Slave receive mode Slave transmit mode SDA Master output SDA Slave output SCL Slave output Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 545: ...2 3 4 5 6 7 8 9 TRS ICDRT A SCL Master output SDA Master output SDA Slave output SCL Slave output Bit 7 Slave transmit mode Slave receive mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A 3 Clear TEND...

Page 546: ...st frame following detection of the start condition the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the ninth clock pulse At the same time RDRF in ICSR is set to r...

Page 547: ...format by setting the FS bit in SAR to 1 When the MST bit in ICCR1 is 1 the transfer clock output from SCL is selected When MST is 0 the external clock input is selected Data Transfer Format Figure 16...

Page 548: ...1 Initial setting 2 Set the TRS bit in ICCR1 to select the transmit mode Then TDRE in ICSR is set 3 Confirm that TDRE has been set Then write the transmit data to ICDRT The data is transferred from I...

Page 549: ...ext byte can be received so the clock is continually output The continuous reception is performed by reading ICDRR every time RDRF is set When the eighth clock is raised while RDRF is 1 the overrun is...

Page 550: ...1 User processing Data 1 Data 1 Data 2 Data 2 Data 3 2 Set MST when outputting the clock 3 Read ICDRR 3 Read ICDRR Figure 16 15 Receive Mode Operation Timing SDA Input Bit 0 1 2 3 4 5 6 7 8 000 Bit 1...

Page 551: ...or SDA input signal is sampled on the system clock When NF2CYC is set to 0 this signal is not passed forward to the next circuit unless the outputs of both latches agree When NF2CYC is set to 1 this s...

Page 552: ...in ICSR Clear TDRE in ICSR End Write transmit data in ICDRT Transmit mode No Yes TDRE 1 Last byte STOP 1 No No No No No Yes Yes TEND 1 Yes Yes Yes 1 Test the status of the SCL and SDA lines 2 Set mast...

Page 553: ...CDDR 4 Wait for 1 byte to be received 5 Check whether it is the last receive 1 6 Read the receive data last 7 Set acknowledge of the final byte Disable continuous reception RCVD 1 8 Read the final byt...

Page 554: ...TEND in ICSR Set TRS in ICCR1 to 0 Dummy read ICDRR Clear TDRE in ICSR End 1 Clear the AAS flag 2 Set transmit data for ICDRT except for the last byte 3 Wait for ICDRT empty 4 Set the last byte of tr...

Page 555: ...device 3 Dummy read ICDRR 4 Wait for 1 byte to be received 5 Check whether it is the last receive 1 6 Read the receive data 7 Set acknowledge of the last byte 8 Read the last byte 1 of receive data 9...

Page 556: ...1 TIE 1 Transmit end TEI TEND 1 TEIE 1 Receive data full RXI RDRF 1 RIE 1 STOP recognition STPI STOP 1 STIE 1 NACK receive Arbitration lost overrun error NAKI NACKF 1 AL 1 NAKIE 1 When the interrupt c...

Page 557: ...sistance Therefore it monitors SCL and communicates by bit with synchronization Figure 16 22 shows the timing of the bit synchronous circuit and table 16 4 shows the time when SCL output changes from...

Page 558: ...rt retransmission or stop condition is attempt to be generated at the specific timing under the following two conditions the start or stop condition may not be generated normally Under conditions othe...

Page 559: ...on of DMA transfer request or interrupt request generation on compare match When not in use CMT can be stopped by halting its clock supply to reduce power consumption Figure 17 1 shows a block diagram...

Page 560: ...R_1 Compare match timer control status register_1 CMCSR_1 Compare match counter_1 CMCNT_1 Compare match timer constant register_1 CMCOR_1 17 2 1 Compare Match Timer Start Register CMSTR CMSTR is a 16...

Page 561: ...always be 0 7 CMF 0 R W Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match 0 CMCNT and CMCOR values do not match Clearing condition When 0 is written to CMF after reading...

Page 562: ...pare Match Counter CMCNT CMCNT is a 16 bit register used as an up counter When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1 CMCNT starts co...

Page 563: ...H 0000 and the CMF flag in CMCSR is set to 1 CMCNT then starts counting up again from H 0000 Figure 17 2 shows the operation of the compare match counter CMCOR H 0000 CMCNT value Time Counter cleared...

Page 564: ...g of CMF bit setting N Peripheral operating clock P Counter clock CMCNT CMCOR Compare match signal Clock N 1 N 0 Figure 17 4 Timing of CMF Setting 17 4 2 DMA Transfer Requests and Interrupt Requests G...

Page 565: ...ction 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 515 of 982 REJ09B0023 0400 17 4 3 Timing of Compare Match Flag Clearing The CMF bit in CMCSR is cleared by first reading as 1 then writing to...

Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...

Page 567: ...Input capture function Counter clear operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous...

Page 568: ..._4 General registers buffer registers TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 I O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D...

Page 569: ...A_4 compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D O...

Page 570: ...imer control register Timer mode register Timer I O control registers H L TIER TSR TCNT TGR A B C D Timer interrupt enable register Timer status register Timer counter Timer general registers A B C D...

Page 571: ...input capture input output compare output PWM output pin 1 TIOC1A I O TGRA_1 input capture input output compare output PWM output pin TIOC1B I O TGRB_1 input capture input output compare output PWM ou...

Page 572: ...r general register B_0 TGRB_0 Timer general register C_0 TGRC_0 Timer general register D_0 TGRD_0 Timer control register_1 TCR_1 Timer mode register_1 TMDR_1 Timer I O control register _1 TIOR_1 Timer...

Page 573: ...O control register H_4 TIORH_4 Timer I O control register L_4 TIORL_4 Timer interrupt enable register_4 TIER_4 Timer status register_4 TSR_4 Timer counter_4 TCNT_4 Timer general register A_4 TGRA_4 Ti...

Page 574: ...ge 1 and 0 These bits select the input clock edge When the input clock is counted using both edges the input clock period is halved e g P 4 both edges 2 rising edge If phase counting mode is used on c...

Page 575: ...ther channel performing synchronous clearing synchronous operation 1 Notes 1 Synchronous operation is set by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is...

Page 576: ...al clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 External clock counts on TCLKD pin input Table 18 6 TPSC0 to TPSC2 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPS...

Page 577: ...rnal clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on P 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 18 8 TPS...

Page 578: ...GRD is used as a buffer register TGRD input capture output compare is not generated In channels 1 and 2 which have no TGRD bit 5 is reserved It is always read as 0 and should only be written with 0 0...

Page 579: ...WM mode 1 transmit at peak 3 1 0 Complementary PWM mode 2 transmit at valley 3 1 Complementary PWM mode 2 transmit at peak and valley 3 Legend X Don t care Notes 1 PWM mode 2 cannot be set for channel...

Page 580: ...output at the point at which the counter is cleared to 0 is specified When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register TIORH...

Page 581: ...e buffer register of TGRB this setting is disabled and input capture output compare does not occur See the following tables TIORL_0 Table 18 11 TIORL_3 Table 18 15 TIORL_4 Table 18 17 3 2 1 0 IOC3 IOC...

Page 582: ...ggle output at compare match 0 Output hold 0 1 Initial output is 1 0 output at compare match 0 Initial output is 1 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 Toggle...

Page 583: ...is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling ed...

Page 584: ...ch 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle...

Page 585: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 586: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 587: ...ompare match 1 0 0 Output hold 1 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input ca...

Page 588: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 589: ...ompare match 1 0 0 Output hold 1 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input ca...

Page 590: ...output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at c...

Page 591: ...t is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 0 0 0 Input capture at rising edge 1 Input capture at falling...

Page 592: ...Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle outp...

Page 593: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 594: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 595: ...ompare match 1 0 0 Output hold 1 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input ca...

Page 596: ...output is 0 1 output at compare match 1 Initial output is 0 Toggle output at compare match 1 0 0 Output hold 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compar...

Page 597: ...compare match 1 0 0 Output hold 1 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Initial output is 1 Toggle output at compare match 1 X 0 0 Input c...

Page 598: ...tart request generation enabled 6 TGFASEL 0 R W TGFA Interrupt DMA Transfer Select Selects the TGFA interrupt request or DMA transfer request when the TGFA flag in TGRA is set to 1 0 Interrupt request...

Page 599: ...to 1 in channels 0 3 and 4 In channels 1 and 2 bit 2 is reserved It is always read as 0 and should only be written with 0 0 Interrupt requests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by T...

Page 600: ...and 4 In channel 0 bit 7 is reserved It is always read as 1 and should only be written with 1 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This bit is always read as 1 The write value should al...

Page 601: ...mode Clearing condition When 0 is written to TCFV after reading TCFV 1 3 TGFD 0 R W Input Capture Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare matc...

Page 602: ...and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register Clearing condition When 0 is written...

Page 603: ...only when a DMA address error occurs during a DMA read cycle 18 3 6 Timer Counter TCNT The TCNT registers are 16 bit readable writable counters The MTU has five TCNT counters one for each channel The...

Page 604: ...utput value 0 TCNT_4 and TCNT_3 count operation is stopped 1 TCNT_4 and TCNT_3 performs count operation 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0...

Page 605: ...hannels 1 TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting synchronous clearing is possible 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should a...

Page 606: ...TIOC4D This bit enables disables the TIOC4D pin MTU output 0 MTU output is disabled 1 MTU output is enabled 4 OE4C 0 R W Master Enable TIOC4C This bit enables disables the TIOC4C pin MTU output 0 MTU...

Page 607: ...e output is disabled 1 Toggle output is enabled 5 to 2 All 0 R Reserved These bits are always read as 0 Only 0 should be written to this bit 1 OLSN 0 R W Output Level Select N This bit selects the rev...

Page 608: ...level High level High level Low level Figure 18 2 shows an example of complementary PWM mode output one phase when OLSN 1 OLSP 1 TCNT_3 and TCNT_4 values TGRA_3 TGRA_4 TDDR H 0000 Time TCNT_4 TCNT_3...

Page 609: ...ld always be 1 6 BDC 0 R W Brushless DC Motor This bit selects whether to make the functions of this register TGCR effective or ineffective 0 Ordinary output 1 Functions of this register are made effe...

Page 610: ...carried out by software TGCR s UF VF WF settings 2 1 0 WF VF UF 0 0 0 R W R W R W Output Phase Switch 2 to 0 These bits set the positive phase negative phase output phase on or off state The setting...

Page 611: ...unt operation starts Note Accessing TDDR in 8 bit units is prohibited Always access in 16 bit units 18 3 15 Timer Period Data Register TCDR TCDR is a 16 bit register used only in complementary PWM mod...

Page 612: ...rs are 8 bit registers These are connected to the CPU by a 16 bit data bus so 16 bit read writes and 8 bit read writes are both possible 18 4 Operation 18 4 1 Basic Functions Each channel has a TCNT a...

Page 613: ...learing source with bits CCLR2 to CCLR0 in TCR 3 Designate the TGR selected in 2 as an output compare register by means of TIOR 4 Set the periodic counter cycle in the TGR selected in 2 5 Set the CST...

Page 614: ...been made TCNT starts up count operation as a periodic counter when the corresponding bit in TSTR is set to 1 When the count value matches the value in TGR the TGF bit in TSR is set to 1 and TCNT is c...

Page 615: ...IOC pin until the first compare match occurs 2 Set the timing for compare match generation in TGR 3 Set the CST bit in TSTR to 1 to start the count operation Figure 18 6 Example of Setting Procedure f...

Page 616: ...er cleared by TGRB compare match Figure 18 8 Example of Toggle Output Operation Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge Rising edge fall...

Page 617: ...R and select rising edge falling edge or both edges as the input capture source and input signal edge 2 Set the CST bit in TSTR to 1 to start the count operation Figure 18 9 Example of Input Capture O...

Page 618: ...Example of Input Capture Operation 18 4 2 Synchronous Operation In synchronous operation the values in a number of TCNT counters can be rewritten simultaneously synchronous presetting Also a number of...

Page 619: ...selection 1 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation 2 When the TCNT counter of any of the channels designated for synchronous operation...

Page 620: ...clearing has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clear...

Page 621: ...register combinations used in buffer operation Table 18 29 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 3 TGRA_3 TGRC_3 TGRB_3...

Page 622: ...general register TCNT Input capture signal Figure 18 14 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 18 15 shows an example of the buffer operation setting proce...

Page 623: ...GRA This operation is repeated each time that compare match A occurs For details of PWM modes see section 18 4 5 PWM Modes TCNT value TGRB_0 H 0000 TGRC_0 TGRA_0 H 0200 H 0520 TIOCA H 0200 H 0450 H 05...

Page 624: ...32 bit counter This function works by counting the channel 1 counter clock upon overflow underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR Underflow occurs only when the lower 16 bit TCNT is in...

Page 625: ...overflow underflow counting 2 Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation Figure 18 18 Cascaded Operation Setting Procedure Examples of Cascaded Operation...

Page 626: ...to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches...

Page 627: ...TGRA_0 TIOC0A TGRB_0 TIOC0A TIOC0B TGRC_0 TIOC0C 0 TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A 1 TGRB_1 TIOC1A TIOC1B TGRA_2 TIOC2A 2 TGRB_2 TIOC2A TIOC2B TGRA_3 Setting prohibited TGRB_3 TIOC3A Setting prohi...

Page 628: ...n output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6...

Page 629: ...ing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 outputting a 5 phase PWM waveform In this case the value set in TGRB_...

Page 630: ...written TGRB rewritten TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty cycle TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches o...

Page 631: ...ns of bits CCLR0 and CCLR1 in TCR and of TIOR TIER and TGR are valid and input capture compare match and interrupt functions can be used This can be used for two phase encoder pulse input If overflow...

Page 632: ...start the count operation Figure 18 24 Example of Phase Counting Mode Setting Procedure Examples of Phase Counting Mode Operation In phase counting mode TCNT counts up or down according to the phase...

Page 633: ...gh level Up count Low level Low level High level High level Down count Low level High level Low level Legend Rising edge Falling edge Phase counting mode 2 Figure 18 26 shows an example of phase count...

Page 634: ...t care Low level Don t care High level Up count High level Don t care Low level Don t care High level Don t care Low level Down count Legend Rising edge Falling edge Phase counting mode 3 Figure 18 2...

Page 635: ...t care Low level Don t care High level Up count High level Down count Low level Don t care High level Don t care Low level Don t care Legend Rising edge Falling edge Phase counting mode 4 Figure 18 2...

Page 636: ...annel 1 is set to phase counting mode 1 and the encoder pulse A phase and B phase are input to TCLKA and TCLKB Channel 0 operates with TCNT counter clearing by TGRC_0 compare match TGRA_0 and TGRC_0 a...

Page 637: ...0400 TCNT_1 TCNT_0 Channel 1 TGRA_1 speed period capture TGRA_0 speed control period TGRB_1 position period capture TGRC_0 position control period TGRB_0 pulse width capture TGRD_0 buffer operation Ch...

Page 638: ...t Pins for Reset Synchronized PWM Mode Channel Output Pin Description 3 TIOC3B PWM output pin 1 TIOC3D PWM output pin 1 negative phase waveform of PWM output 1 4 TIOC4A PWM output pin 2 TIOC4C PWM out...

Page 639: ...rming brushless DC motor control set bit BDC in the timer gate control register TGCR and set the feedback signal input source and output chopping or gate signal direct output Reset TCNT_3 and TCNT_4 t...

Page 640: ...as upcounters The counter is cleared when a TCNT_3 and TGRA_3 compare match occurs and then begins counting up from H 0000 The PWM output pin output toggles with each occurrence of a TGRB_3 TGRA_4 TG...

Page 641: ...d TCNT_3 and TCNT_4 function as increment decrement counters Table 18 39 shows the PWM output pins used Table 18 40 shows the settings of the registers used A function to directly cut off the PWM outp...

Page 642: ...tput 3 compare register Maskable by PTE PEMTURWE setting TGRC_4 PWM output 2 TGRA_4 buffer register Always readable writable TGRD_4 PWM output 3 TGRB_4 buffer register Always readable writable Timer d...

Page 643: ...utput 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE2 POE3 External cutoff input External cutoff interrupt Registers that can always be read or written from the CPU R...

Page 644: ...he timer gate control register TGCR and set the feedback signal input source and output chopping or gate signal direct output Set the dead time in TCNT_3 Set TCNT_4 to H 0000 Set only when restarting...

Page 645: ...TDDR the counter switches to up counting and the operation is repeated in this way TCNT_4 is initialized to H 0000 When the CST bit is set to 1 TCNT4 counts up in synchronization with TCNT_3 and swit...

Page 646: ...e CPU Data in a compare register is changed by writing the new data to the corresponding buffer register The buffer registers can be read or written at any time The data written to a buffer register i...

Page 647: ...NT_3 TCNT_4 and TCNTS and two registers compare register and temporary register are compared and PWM output controlled accordingly TGRA_3 TCDR TGRA_4 TGRC_4 TDDR H 0000 Buffer register TGRC_4 Temporar...

Page 648: ...and TGRD_4 The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set Set TCNT_4 to H 0000 befo...

Page 649: ...TCNT_3 upper limit value is set and TCDR in which the TCNT_4 upper limit value is set The settings should be made so as to achieve the following relationship between these two registers TGRA_3 set val...

Page 650: ...rs to temporary registers when TCNTS is counting in this case the value written to a buffer register is transferred after TCNTS halts The temporary register value is transferred to the compare registe...

Page 651: ...from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare regist...

Page 652: ...value set in the dead time register TDDR Figure 18 38 shows an example of the initial output in complementary PWM mode An example of the waveform when the initial PWM duty value is smaller than the T...

Page 653: ...bit 0 initial output high active level low OLSP bit 0 initial output high active level low TCNT_3 4 value TGR_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3 4 count start TSTR setting Co...

Page 654: ...prior to a are ignored In the T2 period compare match c that turns off the positive phase has the highest priority and compare matches occurring prior to c are ignored In normal cases compare matches...

Page 655: ...Pulse Unit MTU Rev 4 00 Sep 14 2005 Page 605 of 982 REJ09B0023 0400 T2 period T1 period T1 period a b c a b d TGR3A_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 18 40 Example of Complement...

Page 656: ...r Pulse Unit MTU Rev 4 00 Sep 14 2005 Page 606 of 982 REJ09B0023 0400 T2 period T1 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase c d a a b b Figure 18 41 Example of Complement...

Page 657: ...r Pulse Unit MTU Rev 4 00 Sep 14 2005 Page 607 of 982 REJ09B0023 0400 a b c a b d T1 period T2 period T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase Figure 18 42 Example of Complement...

Page 658: ...itive phase with a 100 on state 0 duty output is performed when the data register value is set to the same value as TGRA_3 The waveform in this case has a positive phase with a 100 off state On and of...

Page 659: ...T1 period TGRA_3 TCDR TDDR H 0000 Positive phase Negative phase a c d a b b Figure 18 44 Example of Complementary PWM Mode 0 and 100 Waveform Output 2 T2 period T1 period T1 period a b c d TGRA_3 TCD...

Page 660: ...0000 Positive phase Negative phase T2 period T1 period T1 period a b c b d a Figure 18 46 Example of Complementary PWM Mode 0 and 100 Waveform Output 4 c a d b T2 period T1 period T1 period TGRA_3 TCD...

Page 661: ...ting the PSYE bit to 1 in the timer output control register TOCR An example of a toggle output waveform is shown in figure 18 48 This output is toggled by a compare match between TCNT_3 and TGRA_3 and...

Page 662: ...s clearing with bits CCLR2 to CCLR0 in the timer control register TCR it is possible to have TCNT_3 TCNT_4 and TCNTS cleared by another channel Figure 18 49 illustrates the operation Use of this funct...

Page 663: ...t pin TIOC0A TIOC0B or TIOC0C the output on off state is switched automatically When the FB bit is 1 the output on off state is switched when the UF VF or WF bit in TGCR is cleared to 0 or set to 1 Th...

Page 664: ...TIOC4B pin TIOC4D pin 6 phase output When BCD 1 N 1 P 1 FB 0 output active level high Figure 18 51 Example of Output Phase Switching by External Input 2 TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin...

Page 665: ...els 3 and 4 When start requests using a TGRA_3 compare match are set A D conversion can be started at the center of the PWM pulse A D conversion start requests can be set by setting the TTGE bit to 1...

Page 666: ...ically to the high impedance state by inputting specified external signals There are four external signal input pins See section 18 9 Port Output Enable POE for details 18 5 Interrupts 18 5 1 Interrup...

Page 667: ...3 input capture compare match TGFA_3 Possible TGI3B TGRB_3 input capture compare match TGFB_3 Not possible TGI3C TGRC_3 input capture compare match TGFC_3 Not possible TGI3D TGRD_3 input capture compa...

Page 668: ...ure compare match in each channel the DMA transfer is requested to DMA For details see section 13 Direct Memory Access Controller DMAC A total of five MTU input capture compare match interrupts can be...

Page 669: ...ure 18 55 shows TCNT count timing in external clock operation normal mode and figure 18 56 shows TCNT count timing in external clock operation phase counting mode TCNT TCNT input clock Internal clock...

Page 670: ...the count value matched by TCNT is updated When a compare match signal is generated the output value set in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR...

Page 671: ...N N 1 TGR Compare match signal TIOC pin N Figure 18 58 Output Compare Output Timing Complementary PWM Mode Reset Synchronous PWM Mode Input Capture Signal Timing Figure 18 59 shows input capture signa...

Page 672: ...ws the timing when counter clearing on compare match is specified and figure 18 61 shows the timing when counter clearing on input capture is specified TCNT Counter clear signal Compare match signal T...

Page 673: ...Operation Timing Figures 18 62 and 18 63 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 P Figure 18 62 Buffer Operation Timing Compare Match TGRA TGRB T...

Page 674: ...e match and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt P Figure 18 64 TGI Interrupt Timing Compare Match TGF Flag Setting Timing...

Page 675: ...IV interrupt request signal timing Figure 18 67 shows the timing for setting of the TCFU flag in TSR on underflow and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input cloc...

Page 676: ...is cleared automatically Figure 18 68 shows the timing for status flag clearing by the CPU and figure 18 69 shows the timing for status flag clearing by the DMA Status flag Write signal Address TSR a...

Page 677: ...th edge detection The TPU will not operate properly at narrower pulse widths In phase counting mode the phase difference and overlap between the two input clocks must be at least 1 5 states and the pu...

Page 678: ...ter frequency is given by the following formula f P N 1 Where f Counter frequency P Peripheral clock operating frequency N TGR set value 18 7 4 Conflict between TCNT Write and Clear Operations If the...

Page 679: ...ent Operations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 18 72 shows the timing in this case TCNT input clock Writ...

Page 680: ...are match signal Write signal Address P TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Figure 18 73 Conflict between TGR Write and Compare Match 18 7 7 Conflict between Buffer Reg...

Page 681: ...egister TGR write cycle T1 T2 M TGR N M Buffer register write data Figure 18 74 Conflict between Buffer Register Write and Compare Match Channel 0 P Address Write signal Compare match signal Compare m...

Page 682: ...e signal is generated in the T2 state of a TGR read cycle the data that is read will be that in the buffer after input capture transfer Figure 18 76 shows the timing in this case Input capture signal...

Page 683: ...If an input capture signal is generated in the T2 state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 18 77 shows the timing in this ca...

Page 684: ...erflow Underflow Conflict in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection when a conflict occurs during TCNT_1 count during a TCNT_2 overflow underflow in the T2 stat...

Page 685: ...NT_2 write data TCNT_2 address TCNT write cycle P Address Write signal TCNT_2 TGR2A_2 to TGR2B_2 Ch2 compare match signal A B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare match signal A TGRB_1 Ch1 inp...

Page 686: ...g mode be sure that TCNT_3 and TCNT_4 are set to the initial values TGRA_3 TCDR TDDR H 0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Compl...

Page 687: ...FA and BFB bit settings of TMDR_3 For example if the BFA bit of TMDR_3 is set to 1 TGRC_3 functions as the buffer register for TGRA_3 At the same time TGRC_4 functions as the buffer register for TRGA_...

Page 688: ...h cleared At this point TSR s overflow flag TCFV bit is not set Figure 18 82 shows a TCFV bit operation example in reset sync PWM mode with a set value for cycle register TGRA_3 of H FFFF when a TGRA_...

Page 689: ...TCNT Write and Overflow Underflow If there is an up count or down count in the T2 state of a TCNT write cycle and overflow underflow occurs the TCNT write takes precedence and the TCFV TCFU flag in T...

Page 690: ...itch to normal operation then initialize the output pins to low level output and set an initial register value of H 00 before making the transition to reset synchronous PWM mode 18 7 19 Output Level i...

Page 691: ...method for each of these modes is described in this section 18 8 2 Reset Start Operation The MTU output pins TIOC are initialized to low by a power on reset or in standby mode Since MTU pin function s...

Page 692: ...for restarting in a different mode after re setting are shown below The MTU has six operating modes as stated above There are thus 36 mode transition combinations but some transitions are not availab...

Page 693: ...operate as buffer registers setting TIOR will not initialize the buffer register pins If initialization is required clear buffer mode carry out initialization then set buffer mode again In PWM mode 1...

Page 694: ...h Z High Z Figure 18 85 Error Occurrence in Normal Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 After a reset the TMDR setting is for norm...

Page 695: ...R 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC B High Z High Z MTU module output TIOC A TIOC B Port out...

Page 696: ...T 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized cycle register High Z High Z MTU module output TIOC A TIOC B Port output TIOC A PTE n TIOC B PTE n n 0 to 15 Figure 1...

Page 697: ...3 TOER 1 5 PFC MTU 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 High Z High Z MTU module output TIOC A TIOC B Port ou...

Page 698: ...disabled 13 TOER 0 14 TOCR 15 TMDR CPWM 16 TOER 1 17 PFC MTU 18 TSTR 1 MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3B PTE 6 TIOC3A PTE 7 TIOC3D PTE 4 High Z High Z High Z Figure 18 89 Error...

Page 699: ...init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TIOR 0 init 0 out 12 TIOR disabled 13 TOER 0 14 TOCR 15 TMDR CPWM 16 TOER 1 17 PFC MTU 18 TSTR 1 High Z High Z High Z MTU module outp...

Page 700: ...PTE n TIOC B PTE n n 0 to 15 Figure 18 91 Error Occurrence in PWM Mode 1 Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Set PWM mode 1 3 For chan...

Page 701: ...PFC MTU 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC B Not initialized TIOC B High Z High Z MTU...

Page 702: ...tch 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM2 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC B Not initialized cycle register High Z High Z MTU module output TIOC A TIOC B Port...

Page 703: ...FC MTU 4 TIOR 1 init 0 out 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PCM 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC B High Z High Z MTU module output TIOC A TIOC...

Page 704: ...TU 19 TSTR 1 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3B PTE 6 TIOC3A PTE 7 TIOC3D PTE 4 Figure 18 95 Error Occurrence...

Page 705: ...ror occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TIOR 0 init 0 out 13 TIOR disabled 14 TOER 0 15 TOCR 16 TMDR RPWM 17 TOER 1 18 PFC MTU 19 TSTR 1 Not initialized TIOC3B Not initialized TIOC3D High Z...

Page 706: ...t output TIOC A PTE n TIOC B PTE n n 0 to 15 Figure 18 97 Error Occurrence in PWM Mode 2 Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Set PWM m...

Page 707: ...PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 Not initialized TIOC B Not initialized cycle register Hig...

Page 708: ...ut 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 Not initialized cycle register Not initialized cycle register High Z High Z MTU...

Page 709: ...mode after re setting 1 RESET 2 TMDR PWM2 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 Not initialized cycle...

Page 710: ...TU module output TIOC A TIOC B Port output TIOC A PTE n TIOC B PTE n n 0 to 15 Figure 18 101 Error Occurrence in Phase Counting Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports...

Page 711: ...tting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM1 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 Not initialized TIOC B High Z High Z M...

Page 712: ...RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PWM2 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 High Z High Z Not initialized cycle register M...

Page 713: ...nting mode after re setting 1 RESET 2 TMDR PCM 3 TIOR 1 init 0 out 5 TSTR 1 4 PFC MTU 6 Match 7 Error occurs 8 PFC PORT 9 TSTR 0 10 TMDR PCM 11 TIOR 1 init 0 out 12 PFC MTU 13 TSTR 1 High Z High Z MTU...

Page 714: ...TIOC3A PTE 7 TIOC3D PTE 4 Figure 18 105 Error Occurrence in Complementary PWM Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Select the com...

Page 715: ...CPWM 5 PFC MTU 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z M...

Page 716: ...operation is restarted using the cycle and duty settings at the time the counter was stopped 1 RESET 2 TOCR 3 TMDR CPWM 5 PFC MTU 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC M...

Page 717: ...R 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR CPWM 15 TOER 1 16 PFC MTU 17 TSTR 1 High Z High Z High Z MTU module output TIOC3A TIOC3B TIOC3D Port o...

Page 718: ...9 PFC PORT 10 TSTR 0 11 TMDR normal 12 TOER 0 13 TOCR 14 TMDR RPWM 15 TOER 1 16 PFC MTU 17 TSTR 1 High Z High Z High Z MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3B PTE 6 TIOC3A PTE 7 TIOC...

Page 719: ...ure 18 110 Error Occurrence in Reset Synchronous PWM Mode Recovery in Normal Mode 1 After a reset MTU output is low and ports are in the high impedance state 2 Select the reset synchronous PWM output...

Page 720: ...1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TMDR PWM1 12 TIOR 1 init 0 out 13 PFC MTU 14 TSTR 1 Not initialized TIOC3B Not initialized TIOC3D High Z High Z High Z MTU module output TIOC...

Page 721: ...7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 TOER 0 12 TOCR 13 TMDR CPWM 14 TOER 1 15 PFC MTU 16 TSTR 1 High Z High Z High Z MTU module output TIOC3A TIOC3B TIOC3D Port output TIOC3B PTE 6 TIOC3A P...

Page 722: ...chronous PWM mode after re setting 1 RESET 2 TOCR 3 TMDR RPWM 5 PFC MTU 4 TOER 1 6 TSTR 1 7 Match 8 Error occurs 9 PFC PORT 10 TSTR 0 11 PFC MTU 12 TSTR 1 13 Match High Z High Z High Z High Z High Z H...

Page 723: ...IOC4C PTE 1 TIOC4D PTE 0 It can also simultaneously generate interrupt requests 18 9 1 Features Each of the POE0 to POE3 input pins can be set for falling edge P 8 16 P 16 16 or P 128 16 low level sam...

Page 724: ...TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D POE3 POE2 POE1 POE0 Output level detection circuit Output level detection circuit Output level detection circuit Input level detection circuit Falling edge detection...

Page 725: ...TE 3 and TIOC4C PTE 1 Output All high current pins are made high impedance state when the pins simultaneously output low level for longer than 1 cycle TIOC4B PTE 2 and TIOC4D PTE 0 Output All high cur...

Page 726: ...has been input to the POE2 pin Clear condition By writing 0 to POE2F after reading a POE2F 1 Set condition When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin 13 POE1F 0 R W POE1 Flag Thi...

Page 727: ...ling edge of POE3 input 01 Accept request when POE3 input has been sampled for 16 P 8 clock pulses and all are low level 10 Accept request when POE3 input has been sampled for 16 P 16 clock pulses and...

Page 728: ...mpled for 16 P 16 clock pulses and all are low level 11 Accept request when POE1 input has been sampled for 16 P 128 clock pulses and all are low level 1 0 POE0M1 POE0M0 0 0 R W R W POE0 mode 1 0 Thes...

Page 729: ...s set to 1 the high current pins become high impedance Bit Bit Name Initial value R W Description 15 OSF 0 R W Output Short Flag This flag indicates that any one pair of the three pairs of 2 phase out...

Page 730: ...hen using pins as outputs When the OCE bit is set to 1 if OIE 0 a high impedance request will not be issued even if OSF is set to 1 Therefore in order to have a high impedance request issued according...

Page 731: ...the high impedance state 1 Falling Edge Detection When a change from high to low level is input to the POE0 to POE3 pins all high current pins become high impedance state Figure 18 115 shows the timi...

Page 732: ...etection P Sampling clock 3 POE input TIOC3B PTE 6 When low level is sampled at all points When high level is sampled at least once Flag set POE received Flag not set Hi Z state Note Other high curren...

Page 733: ...lags of the ICSR1 High current pins that have become high impedance due to output level detection can be released either by returning them to their initial state with a power on reset or by first clea...

Page 734: ...Section 18 Multi Function Timer Pulse Unit MTU Rev 4 00 Sep 14 2005 Page 684 of 982 REJ09B0023 0400...

Page 735: ...us serial system There are eight selectable serial data communication formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd or none Receive error detection Parity framing and ove...

Page 736: ...controller DMAC can be activated to execute a data transfer by a transmit FIFO data empty or receive FIFO data full interrupt When the SCIF is not in use it can be stopped by halting the clock suppli...

Page 737: ...erator Clock External clock P P 4 P 16 P 64 TXI RXI ERI BRI SCIF Bus interface Internal data bus SCSCR SCSPTR SCRSR SCFRDR SCTSR SCFTDR SCSMR SCSCR Legend SCFSR SCBRR SCSPTR SCFCR SCFDR SCLSR Receive...

Page 738: ...utput Transmit data output Request to send pin RTS0 I O Request to send 0 Clear to send pin CTS0 I O Clear to send Serial clock pin SCK1 I O Clock I O Receive data pin RxD1 Input Receive data input Tr...

Page 739: ...SCFDR_0 Serial port register_0 SCSPTR_0 Line status register_0 SCLSR_0 Receive FIFO data register_1 SCFRDR_1 Transmit FIFO data register_1 SCFTDR_1 Serial mode register_1 SCSMR_1 Serial control regis...

Page 740: ...eive shift register SCRSR into SCFRDR for storage Continuous reception is possible until 16 bytes are stored The CPU can read but not write to SCFRDR If data is read when there is no receive data in t...

Page 741: ...a can be written If writing of new data is attempted the data is ignored SCFTDR is initialized to undefined value by a power on reset Bit Bit Name Initial value R W Description 7 to 0 Undefined W FIFO...

Page 742: ...is selected the MSB bit 7 of the transmit FIFO data register is not transmitted 5 PE 0 R W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data i...

Page 743: ...in the received character and parity bit combined 2 If odd parity is selected the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined...

Page 744: ...ead as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 0 Select the internal clock source of the on chip baud rate generator Four clock sources are available P P 4 P 16 a...

Page 745: ...t Enable Enables or disables the transmit FIFO data empty interrupt TXI requested when the serial transmit data is transferred from the transmit FIFO data register SCFTDR to the transmit shift registe...

Page 746: ...terrupt ERI and break interrupt BRI requests are disabled 1 Receive data full interrupt RXI receive error interrupt ERI and break interrupt BRI requests are enabled Note RXI interrupt requests can be...

Page 747: ...mat in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1 3 REIE 0 R Receive Error Interrupt Enable Enables or disables the receive error ERI interrupts and break BRI interrupts The set...

Page 748: ...ock input If the serial clock output is set in synchronous mode the communication mode bit C A in SCSMR2 is set to 1 and then CKE1 and CKE0 bits are set Asynchronous mode 00 Internal clock SCK pin use...

Page 749: ...en SCFSR is initialized to H 0060 by a power on reset Bit Bit Name Initial value R W Description 15 14 13 12 PER3 PER2 PER1 PER0 0 0 0 0 R R R R Number of Parity Errors Indicate the quantity of data i...

Page 750: ...ions ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation 2 ER is set to 1 when the total number of...

Page 751: ...is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR 1 End of transmission Setting conditions TEND is set to 1 when the chip is a power on reset TEND i...

Page 752: ...cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from TDFE and then 0 is written TDFE is cleared to 0 when DMAC write data exceeding the...

Page 753: ...h space 0 in the subsequent receive data Note When a break is detected transfer of the receive data H 00 to SCFRDR stops after detection When the break ends and the receive signal becomes mark 1 the t...

Page 754: ...FO data register SCFRDR in asynchronous mode 0 No receive parity error occurred in the next data read from SCFRDR Clearing conditions PER is cleared to 0 when the chip undergoes a power on reset PER i...

Page 755: ...0 when the SCFRDR is read until the quantity of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written RDF is cleared to 0 when DM...

Page 756: ...ss or no receive data remains in SCFRDR after receiving ended normally Clearing conditions DR is cleared to 0 when the chip undergoes a power on reset DR is cleared to 0 when all receive data are read...

Page 757: ...t Each channel has independent baud rate generator control so different values can be set in three channels The SCBRR setting is calculated as follows Asynchronous mode N 106 1 64 22n 1 B P Synchronou...

Page 758: ...0 1200 0 129 0 16 0 155 0 16 0 159 0 00 2400 0 64 0 16 0 77 0 16 0 79 0 00 4800 0 32 1 36 0 38 0 16 0 39 0 00 9600 0 15 1 73 0 19 2 34 0 19 0 00 19200 0 7 1 73 0 9 2 34 0 9 0 00 31250 0 4 0 00 0 5 0 0...

Page 759: ...39 0 00 0 47 0 00 19200 0 15 1 73 0 19 0 16 0 19 0 00 0 23 0 00 31250 0 9 0 00 0 11 0 00 0 11 2 40 0 14 1 70 38400 0 7 1 73 0 9 2 34 0 9 0 00 0 11 0 00 P MHz 16 19 6608 20 24 Bit Rate bits s n N Erro...

Page 760: ...39 300 2 159 0 00 2 186 0 08 2 194 0 16 2 214 0 07 600 2 79 0 00 2 92 0 46 2 97 0 35 2 106 0 39 1200 1 159 0 00 1 186 0 08 1 194 0 16 1 214 0 07 2400 1 79 0 00 1 92 0 46 1 97 0 35 1 106 0 39 4800 0 15...

Page 761: ...124 3 223 3 233 3 255 1k 2 77 2 124 2 249 3 111 3 116 3 125 2 5k 1 124 1 199 2 99 2 178 2 187 2 200 5k 0 249 1 99 1 199 2 89 2 93 2 100 10k 0 124 0 199 1 99 1 178 1 187 1 200 25k 0 49 0 79 0 159 1 71...

Page 762: ...9 6 and 19 7 list the maximum rates for external clock input Table 19 5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings P MHz Maximum Bit Rate bits s n N...

Page 763: ...0 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 3...

Page 764: ...power on reset Bit Bit Name Initial value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R W R W R W RTS...

Page 765: ...8 11 14 5 4 TTRG1 TTRG0 0 0 R W R W Transmit FIFO Data Trigger 1 0 Set the quantity of remaining transmit data which sets the transmit FIFO data register empty TDFE flag in the serial status register...

Page 766: ...isabled 1 Reset operation enabled Note Reset operation is executed by a power on reset 1 RFRST 0 R W Receive FIFO Data Register Reset Disables the receive data in the receive FIFO data register and re...

Page 767: ...e the quantity of non transmitted data stored in SCFTDR H 00 means no transmit data and H 10 means that SCFTDR is full of transmit data 7 to 5 All 0 R Reserved These bits are always read as 0 The writ...

Page 768: ...RTS pin Whenever input or output RTS pin status is read from RTSDT bit However Port Function of PFC Pin Function Controller must be set to RTS input output 0 Input output data is low level 1 Input out...

Page 769: ...rt Function of PFC Pin Function Controller must be set to SCK input output 0 Input output data is low level 1 Input output data is high level 1 SPB2IO 0 R W Serial Port Break Input Output Indicates th...

Page 770: ...f an overrun error 0 Receiving is in progress or has ended normally 1 Clearing conditions ORER is cleared to 0 when the chip is a power on reset ORER is cleared to 0 when 0 is written after 1 is read...

Page 771: ...selections constitutes the communication format and character length In receiving it is possible to detect framing errors parity errors receive FIFO data full overrun errors receive data ready and br...

Page 772: ...et 1 bit 1 2 bits 1 0 Set 1 bit 1 Asynchronous 2 bits 1 Synchronous 8 bits Not set None Note Don t care Table 19 9 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR SCSCR Settings SCIF Tr...

Page 773: ...serial communication the communication line is normally held in the mark high state The SCIF monitors the line and starts serial communication when the line goes to the space low state indicating a st...

Page 774: ...STOP 1 0 0 START 7 bit data STOP 1 0 1 START 7 bit data STOP STOP 1 1 0 START 7 bit data P STOP 1 1 1 START 7 bit data P STOP STOP Legend START Start bit STOP Stop bit P Parity bit Clock An internal c...

Page 775: ...shift register SCTSR Clearing TE and RE to 0 however does not initialize the serial status register SCFSR transmit FIFO data register SCFTDR or receive FIFO data register SCFRDR which retain their pre...

Page 776: ...nd set TIE RIE and REIE bits End of initialization Wait No Yes Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresp...

Page 777: ...t data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and read 1 from the TDFE and TEND flags then clear to 0 The number of transmit data bytes that can b...

Page 778: ...ol register SCFCR the TDFE flag is set If the TIE bit in the serial control register SCSR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit dat...

Page 779: ...interrupt request Figure 19 5 Example of Transmit Operation 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS input va...

Page 780: ...BRK flags in SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also...

Page 781: ...No Overrun error handling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in...

Page 782: ...shift register SCRSR to SCFRDR C Overrun check The SCIF checks that the ORER flag is 0 indicating that the overrun error has not occurred D Break check The SCIF checks that the BRK flag is 0 indicatin...

Page 783: ...en RTS is 1 this indicates that SCFRDR exceeds the number set for the RTS output active trigger Figure 19 10 shows an example of the operation when modem control is used D0 D1 D2 D7 0 1 D0 D1 D7 0 1 1...

Page 784: ...k Transmit Receive Formats The data length is fixed at eight bits No parity bit can be added Clock An internal clock generated by the on chip baud rate generator or an external clock input from the SC...

Page 785: ...and REIE bits End of initialization Wait No Yes Leave the TE and RE bits cleared to 0 until the initialization almost ends Be sure to clear the TIE RIE TE and RE bits to 0 Set the data transfer forma...

Page 786: ...0 All data transmitted Read TEND flag in SCFSR TEND 1 Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes 1 SCIF status check and transmit data write Read SCFSR and check that the TDF...

Page 787: ...set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated If clock output mode is selected the SCIF outputs eight synchronous clock pulses If an external clock source is sele...

Page 788: ...in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Reception cannot be resumed while the ORER flag is set to 1 2 SCIF status check and receive data re...

Page 789: ...tion Interface with FIFO SCIF Rev 4 00 Sep 14 2005 Page 739 of 982 REJ09B0023 0400 Error handling Clear ORER flag in SCLSR to 0 End Overrun error handling ORER 1 Yes No Figure 19 16 Sample Flowchart f...

Page 790: ...cted further reception is prevented 3 After setting RDF to 1 if the receive data full interrupt enable bit RIE is set to 1 in SCSCR the SCIF requests a receive data full interrupt RXI If the ORER bit...

Page 791: ...ag from 0 to 1 can also be identified by a TXI interrupt 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0...

Page 792: ...o 1 an RXI interrupt request and receive FIFO data full DMA transfer request are generated When RXI request is disabled by RIE bit and the RDF or DR flag in SCFSR is set to 1 receive FIFO data full DM...

Page 793: ...tes in SCFTDR can be written allowing efficient continuous transmission However if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number the TDFE flag will be...

Page 794: ...rt register SCSPTR This feature can be used to send a break signal Until TE bit is set to 1 enabling transmission after initializing TxD pin does not work During the period mark status is performed by...

Page 795: ...mpling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1 Equation 1 M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N Where M Receive margin N Rati...

Page 796: ...Clock DMA Transfer Request When a DMA transfer is requested from the SCIF of which transfer request is allowed by the DMAC the transfer request from the SCIF is held in the DMAC This transfer request...

Page 797: ...o Control OUT 8 8 Endpoint 1 EP1 Bulk OUT 64 128 Possible Endpoint 2 EP2 Bulk IN 64 128 Possible Endpoint 3 EP3 Interrupt 8 8 Endpoint 1 Endpoint 2 Endpoint 3 Configuration 1 Interface 0 Alternate set...

Page 798: ...on and Functions Pin Name I O Function XVEROFF Conditions XVDATA Input Input pin for receive data from differential receiver 1 DPLS Input Input pin to driver for D signal from receiver 1 DMNS Input In...

Page 799: ...2 USBIFR2 USB interrupt select register 0 USBISR0 USB interrupt select register 1 USBISR1 USB interrupt enable register 0 USBIER0 USB interrupt enable register 1 USBIER1 USB interrupt enable register...

Page 800: ...signal is detected on the USB bus 6 EP1FULL 0 R EP1 FIFO Full This bit is set when endpoint 1 receives one packet of data normally from the host and holds a value of 1 as long as there is valid data...

Page 801: ...s transmitted to the host from endpoint 0 and an ACK handshake is returned 20 3 2 USB Interrupt Flag Register 1 USBIFR1 Together with USB interrupt flag registers 0 USBIFR0 and 2 USBIFR2 USBIFR1 indic...

Page 802: ...3 USB Interrupt Flag Register 2 USBIFR2 Together with USB interrupt flag registers 0 USBIFR0 and 1 USBIFR1 USBIFR2 indicates interrupt status information required by the application When an interrupt...

Page 803: ...the USB issues an interrupt request to the INTC when the corresponding bit in USBISR0 is cleared to 0 the interrupt will be USI0 USB interrupt 0 If the USB issues an interrupt request to the INTC when...

Page 804: ...3 All 0 R Reserved The write value should always be 0 2 EP3TR 0 R W EP3 transfer request 1 EP3TS 0 R W EP3 transmission completion 0 VBUSF 0 R W USB bus connection 20 3 6 USB Interrupt Enable Register...

Page 805: ...t Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved The write value should always be 0 2 EP3TR 0 R W EP3 transfer request 1 EP3TS 0 R W EP3 transmit completion 0 VBUS 0 R W USB bus connec...

Page 806: ...R Bit Bit Name Initial Value R W Description 7 to 0 D7 to D0 Undefined W Data register for control IN transfer 20 3 10 USBEP0o Data Register USBEPDR0o USBEPDR0o is an 8 byte receive FIFO buffer for en...

Page 807: ...s invalid Bit Bit Name Initial Value R W Description 7 to 0 D7 to D0 Undefined R Register for storing the setup command on control OUT transfer 20 3 12 USBEP1 Data Register USBEPDR1 USBEPDR1 is a 128...

Page 808: ...7 to 0 bits for DMA transfer 20 3 14 USBEP3 Data Register USBEPDR3 USBEPDR3 is an 8 byte transmit FIFO buffer for endpoint 3 holding one packet of transmit data in endpoint 3 interrupt transfer Transm...

Page 809: ...for each endpoint USBTRG can be initialized to H 00 by a power on reset Bit Bit Name Initial Value R W Description 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 EP3...

Page 810: ...eceived 0 EP0iPKTE 0 W EP0i Packet Enable After one packet of data has been written to the endpoint 0 transmit FIFO buffer the transmit data is fixed by writing 1 to this bit 20 3 18 USB Data Status R...

Page 811: ...FO buffer The corresponding interrupt flag is not cleared Do not clear a FIFO buffer during transmission reception USBFCLR can be initialized to H 00 by a power on reset Bit Bit Name Initial Value R W...

Page 812: ...W Description 7 to 2 All 0 R Reserved The write value should always be 0 1 EP2DMAE 0 R W Endpoint 2 DMA Transfer Enable When this bit is set DMA transfer is enabled from memory to the endpoint 2 trans...

Page 813: ...the endpoints on the application side While a bit is set to 1 the corresponding endpoint returns a stall handshake to the host The stall bit for endpoint 0 EP0STL is cleared automatically on receptio...

Page 814: ...ate 20 3 22 USB Transceiver Control Register USBXVERCR The USB transceiver control register USBXVERCR selects the on chip transceiver or the external transceiver Make sure to check if USBIFR1 VBUSMN 0...

Page 815: ...control method see section 20 9 USB Bus Power Control Method USBCTRL can be initialized to H 00 by a power on reset Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved The write value...

Page 816: ...preparations are completed enable D pull up in general output port Clear VBUS flag USBIFR1 VBUS Firmware preparations for start of USB communication Clear bus reset flag USBIFR0 BRST Clear FIFOs EP0...

Page 817: ...ried out using IRQx or a general input port For details see section 20 8 Example of USB External Circuitry 20 4 2 Cable Disconnection USB function Application Cable connected VBUS pin 1 USB cable disc...

Page 818: ...us figure 20 4 The data stage comprises a number of bus transactions Operation flowcharts for each stage are shown below Control IN Setup stage Data stage Status stage Control OUT No data SETUP 0 DATA...

Page 819: ...ata stage direction 1 Write 1 to EP0s read complete bit USBTRG EP0s RDFN 1 To control in data stage To control out data stage Command to be processed by application Interrupt request Yes No Notes 1 In...

Page 820: ...st Set EP0i transmission complete flag USBIFR0 EP0i TS 1 From setup stage Write data to USBEP0i data register USBEPDR0i Write 1 to EP0i packet enable bit USBTRG EP0i PKTE 1 Clear EP0i transmission com...

Page 821: ...bit empties the receive FIFO and waits for reception of the next data The end of the data stage is identified when the host transmits an IN token and the status stage is entered USB function Applicati...

Page 822: ...s 0 byte data from the host and ends control transfer USB function Application OUT token reception 0 byte reception from host End of control transfer Set EP0o reception complete flag USBIFR0 EP0o TS 1...

Page 823: ...a is written to the EP0i FIFO As a result the next IN token causes 0 byte data to be transmitted to the host and control transfer ends After the application has finished all processing relating to the...

Page 824: ...reception is completed the USBIFR0 EP1 FULL bit is set After the first receive operation into one of the FIFOs when both FIFOs are empty the other FIFO is empty and so the next packet can be received...

Page 825: ...O full status USBIFR0 EP1 FULL 1 Clear EP1 FIFO full status USBIFR0 EP1 FULL 0 Read USBEP1 receive data size register USBEPSZ1 Read data from USBEP1 data register USBEPDR1 Write 1 to EP1 read complete...

Page 826: ...h this interrupt 1 is written to the USBIER0 EP2EMPTY bit and the EP2 FIFO empty interrupt is enabled At first both EP2 FIFOs are empty and so an EP2 FIFO empty interrupt is generated immediately The...

Page 827: ...EP2 FIFO empty interrupt USBIER0 EP2 EMPTY 1 USBIER0 EP2 EMPTY interrupt Write one packet of data to USBEP2 data register USBEPDR2 Write 1 to EP2 packet enable bit USBTRG EP2 PKTE 1 Set EP2 empty stat...

Page 828: ...rite data to USBEP3 data register USBEPDR3 Write 1 to EP3 packet enable bit USBTRG EP3 PKTE 1 Valid data in EP3 FIFO Is there data for transmission to host Is there data for transmission to host No Ye...

Page 829: ...ce Get status Set address Set configuration Set feature Set interface Get Descriptor Synch Frame Set Descriptor Class Vendor command If decoding is not necessary on the application side command decodi...

Page 830: ...he corresponding bit in USBEPSTL 1 1 in figure 20 13 The internal status bits are not changed When a transaction is sent from the host for the endpoint for which the USBEPSTL bit was set the USB funct...

Page 831: ...from host 2 USBEPSTL referenced 1 Transmission of STALL handshake 1 Internal status bit cleared to 0 1 Internal status bit cleared to 0 2 USBEPSTL not changed 1 1 set in USBEPSTL 2 Internal status bi...

Page 832: ...us bit is set it remains set until cleared by a Clear Feature command from the host without regard to USBEPSTL register After a bit is cleared by the Clear Feature command USBEPSTL is referenced 3 1 i...

Page 833: ...ecification violation etc USB function module stalls endpoint automatically 1 Transmission of STALL handshake 1 Internal status bit cleared to 0 2 USBEPSTL not changed 1 USBEPSTL cleared to 0 by appli...

Page 834: ...n the maximum number of bytes 64 bytes is written to the FIFO and then the data in the FIFO is transmitted See figures 20 15 and 20 16 20 7 1 DMA Transfer for Endpoint 1 If the received data for EP1 i...

Page 835: ...150 bytes of data are transmitted to the host the equivalent processing if writing 1 to the USBTRG PKTE bit is automatically performed internally in the two places in figure 20 16 This processing is d...

Page 836: ...te D and D are pull down on the host or hub side and the USB module recognizes as if the USB bus reset has been received from the host In that case the D pull up control signal and VBUS pin input sign...

Page 837: ...that allows voltage application when the system LSI power is off This LSI USB connector USB cable VBUS VBUS GND D D D D 5 V Note Operation cannot be guaranteed by this example When the system requires...

Page 838: ...n the system LSI power is off USB connector USB cable VBUS VBUS TXENL TXDMNS TXDPLS XVDATA DPLS GND DMNS SUSPND SUSPND PDIUSBP11 etc VM VP RCV OE SPEED VMO VPO D D Note Operation cannot be guaranteed...

Page 839: ...In this LSI an interrupt by detecting the USB suspend signal or awake signal can be shared with an IRQ0 or IRQ1 interrupt by specifying USBCTRL SUSPEND 1 See figure 20 19 This causes an IRQ1 interrup...

Page 840: ...cuitry USBIFR2 SUSPS cleared USBIFR2 AWAKE cleared IRQ0 interrupt detected RTE instruction RTE instruction Peripheral clock IRQ1_USB SUSPEND IRQ0_ AWAKE Normal operation IRQ1 interrupt routine Standby...

Page 841: ...C IRQ0 of INTC to 15 set the priority of IRQ0 to 15 Set IPRC IRQ1 of INTC to 14 set the priority of IRQ1 to 14 Clear ICR1 IRQ00S and IRQ01S of INTC to 0 set the IRQ0 falling edge detection Clear ICR1...

Page 842: ...SSR and SPC to memory Set STBCR STBY SLEEP instruction Set SR I 3 0 to the IRQ1 priority Clear IRR0 IRQ0R of INTC RTE instruction Clear USBIFR2 SUSPS and AWAKE clear detection of USB suspend and AWAKE...

Page 843: ...l state or standby mode Clear IRR0 IRQ0R of INTC Clear IRR0 IRQ1R of INTC Clear USBIFR2 SUSPS and AWAKE Set SR I 3 0 to the IRQ0 priority RTE instruction RTE instruction RTE instruction Restore SSR an...

Page 844: ...data from or to the host 20 10 3 Overreading or Overwriting Data Register Note that the following when reading or writing the data register of this module Receive Data Register Do not read the number...

Page 845: ...ion cannot be guaranteed 20 10 7 USB Clock Input the USB clock UCLK before setting the register in this module 20 10 8 Using TR Interrupt Note that the following when using the transfer request interr...

Page 846: ...0400 TR interrupt routine TR interrupt routine CPU USB Clear TR flag Write transmit data and TRG PKTE IN token Check NAK Set TR flag Host NAK IN token Check NAK Set TR flag flag is set again NAK IN to...

Page 847: ...P 33 MHz operation Three conversion modes Single mode A D conversion on one channel Multi mode A D conversion on one to four channels Scan mode Continuous A D conversion on one to four channels Conve...

Page 848: ...l status register A D 1 data register A A D 1 data register B A D 1 data register C A D 1 data register D 10 bit A D ADDRA1 ADDRB1 ADDRC1 ADDRD1 Bus interface bus Peripheral data bus Analog multi plec...

Page 849: ...age pin AVSS also functions as the A D converter reference ground pin Table 21 1 A D Converter Pins Pin Name Abbreviation I O Function Analog power supply pin AVcc Input Analog power supply and refere...

Page 850: ...er Descriptions 21 2 1 A D Data Registers A to D ADDRA0 to ADDRD0 ADDRA1 to ADDRD1 The eight A D data registers ADDRA0 to ADDRD0 ADDRA1 to ADDRD1 are 16 bit read only registers that store the results...

Page 851: ...ls the A D converter and enable or disable starting of A D conversion by external trigger input ADCSR is initialized to H 0040 by a power on reset and in standby mode Bit Bit Name Initial Value R W De...

Page 852: ...cted channels Multi mode A D conversion starts when conversion is completed cycling through the selected channels ADST is automatically cleared Scan mode A D conversion starts and continues A D conver...

Page 853: ...rsion time Clear the ADST bit to 0 before changing the conversion time 00 Conversion time 151 states maximum clock P 4 01 Conversion time 285 states maximum clock P 8 10 Conversion time 545 states max...

Page 854: ...g 0 21 2 3 A D0 A D1 Control Register ADCR ADCR is a 16 bit readable writable register that selects the simultaneous sampling of two channels See section 21 3 4 Simultaneous Sampling Operation for det...

Page 855: ...it to 0 to halt A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical...

Page 856: ...ore channels When the ADST bit is set to 1 by software A D conversion starts on the first channel in the group A D0 when AN0 A D1 when AN4 When two or more channels are selected after conversion of th...

Page 857: ...Conversion proceeds in the same way through the third channel AN2 5 When conversion of all selected channels AN0 to AN2 is completed the ADF flag is set to 1 and ADST bit is cleared to 0 If the ADIE b...

Page 858: ...l operations when three channels AN0 to AN2 are selected in scan mode are described next Figure 21 4 shows a timing diagram for this example 1 Scan modes are selected analog input channels AN0 to AN2...

Page 859: ...Operation Scan Mode Channels AN0 to AN2 Selected 21 3 4 Simultaneous Sampling Operation With simultaneous sampling conversion is conducted with sampling of the input voltages on two channels channel i...

Page 860: ...ng from setting of the ADST bit until the start of A D conversion is the same as when 1 is written to the ADST bit by software 21 3 6 Input Sampling and A D Conversion Time The A D converter has a bui...

Page 861: ...Conversion Timing Table 21 3 A D Conversion Time Single Mode CKS1 1 CKS0 1 CKS1 1 CKS0 1 CKS1 1 CKS0 1 Symbol Min Typ Max Min Typ Max Min Typ Max A D conversion start delay tD 18 21 10 13 6 9 Input s...

Page 862: ...se requests are enabled or disabled by the ADIE bit or the DMASL bit in ADCSR When the DMAC is activated by an ADI interrupt the ADF bit in the A D control status register ADCSR0 and ADCSR1 is automat...

Page 863: ...been simplified to 3 bits Offset error is the deviation between actual and ideal A D conversion characteristics when the digital output value changes from the minimum zero voltage 0000000000 000 in t...

Page 864: ...ntization error 4 Nonlinearity error 2 Full scale error Ideal A D conversion characteristic Digital output FS Full scale voltage FS Analog input voltage Actual A D convertion characteristic 1 Offset e...

Page 865: ...d according to actual application conditions Section 25 4 A D Converter Characteristics in section 25 Electrical Characteristics shows the analog input pin specifications and figure 21 8 shows an equi...

Page 866: ...program during A D conversion 2 In multi mode or scan mode when A D conversion is stopped with a program during A D conversion write 0 only to the ADST bit If the ADST bit and the other bits are set s...

Page 867: ...dance Figure 21 7 Example of Analog Input Protection Circuit AN0 to AN7 3 k 20 pF to A D converter Note Value are referene value Figure 21 8 Analog Input Pin Equivalent Circuit Sensor input This LSI S...

Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...

Page 869: ...address bus PTA11 input output port A22 output address bus PTA10 input output port A21 output address bus PTA9 input output port A20 output address bus PTA8 input output port A19 output address bus PT...

Page 870: ...output port CS5B output BSC PTC1 input output port CS5A output BSC PTC0 input output port CS4 output BSC D PTD15 input output port D31 input output data bus PTD14 input output port D30 input output d...

Page 871: ...t TIOC3B input output MTU PTE5 input output port TIOC3C input output MTU PTE4 input output port TIOC3D input output MTU PTE3 input output port TIOC4A input output MTU PTE2 input output port TIOC4B inp...

Page 872: ...input port AN1 input ADC PTG0 input port AN0 input ADC H PTH14 input output port RTS2 input output SCIF2 PTH13 input output port RXD2 input SCIF2 PTH12 input output port TXD2 output SCIF2 PTH11 input...

Page 873: ...PTJ5 input output port IRQ5 input INTC PTJ4 input output port IRQ4 input INTC PTJ3 input output port IRQ3 input INTC PTJ2 input output port IRQ2 input INTC PTJ1 input output port IRQ1 input INTC PTJ0...

Page 874: ...ead as 0 The write value should always be 0 29 28 PA14MD2 PA14MD1 0 0 R W R W 27 26 PA13MD2 PA13MD1 0 0 R W R W 25 24 PA12MD2 PA12MD1 0 0 R W R W 23 22 PA11MD2 PA11MD1 0 0 R W R W 21 20 PA10MD2 PA10MD...

Page 875: ...The combination of bits PAnMD2 and PAnMD1 n 0 to 14 controls the pin functions 00 Port input 01 Port output 10 Reserved When set correct operation cannot be guaranteed 11 Other functions see table 22...

Page 876: ...18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 16 PB8MD2 PB8MD1 0 0 R W R W 15 14 PB7MD2 PB7MD1 0 0 R W R W 13 12 PB6MD2 PB6MD1 0 0 R W R W 11 10 PB5MD2 PB5M...

Page 877: ...5MD1 0 0 R W R W 29 28 PC14MD2 PC14MD1 0 0 R W R W 27 26 PC13MD2 PC13MD1 1 1 R W R W 25 24 PC12MD2 PC12MD2 0 0 R W R W 23 22 PC11MD2 PC11MD1 0 0 R W R W 21 20 PC10MD2 PC10MD1 0 0 R W R W 19 18 PC9MD2...

Page 878: ...er that selects the pin functions PDCR is initialized to H 00000000 MD3 0 16 bit bus width or H FFFFFFFF MD3 1 32 bit bus width by a power on reset and it is not initialized by a manual reset in stand...

Page 879: ...1 R W R W 11 10 PD5MD2 PD5MD1 0 1 0 1 R W R W 9 8 PD4MD2 PD4MD1 0 1 0 1 R W R W 7 6 PD3MD2 PD3MD1 0 1 0 1 R W R W 5 4 PD2MD2 PD2MD1 0 1 0 1 R W R W 3 2 PD1MD2 PD1MD1 0 1 0 1 R W R W 1 0 PD0MD2 PD0MD1...

Page 880: ...0 0 R W R W 25 24 PE12MD2 PE12MD1 0 0 R W R W 23 22 PE11MD2 PE11MD1 0 0 R W R W 21 20 PE10MD2 PE10MD1 0 0 R W R W 19 18 PE9MD2 PE9MD1 0 0 R W R W 17 16 PE8MD2 PE8MD1 0 0 R W R W 15 14 PE7MD2 PE7MD1 0...

Page 881: ...1MD1 0 0 R W R W 1 0 PE0MD2 PE0MD1 0 0 R W R W PEn Mode 2 and 1 The combination of bits PEnMD2 and PEnMD1 n 0 to 15 controls the pin functions 00 Port input 01 Port output 10 Reserved When set correct...

Page 882: ...etting a bit in PEIOR to 0 sets the pin to input PEIOR is initialized to H 0000 by a power on reset and it is not initialized by a manual reset in standby mode or in sleep mode Bit Bit Name Initial Va...

Page 883: ...ialized to H 0001 by a power on reset and it is not initialized by a manual reset in standby mode or in sleep mode Bit Bit Name Initial Value R W Description 15 to 1 All 0 R Reserved These bits are al...

Page 884: ...de Bit Bit Name Initial Value R W Description 31 30 PF15MD2 PF15MD1 0 0 R W R W 29 28 PF14MD2 PF14MD1 0 0 R W R W 27 26 PF13MD2 PF13MD1 0 0 R W R W 25 24 PF12MD2 PF12MD2 0 0 R W R W 23 22 PF11MD2 PF11...

Page 885: ...6MD2 0 0 R W R W 11 10 PF5MD2 PF5MD2 0 0 R W R W 9 8 PF4MD2 PF4MD2 0 0 R W R W 7 6 PF3MD2 PF3MD2 0 0 R W R W 5 4 PF2MD2 PF2MD2 0 0 R W R W 3 2 PF1MD2 PF1MD2 0 0 R W R W 1 0 PF0MD2 PF0MD2 0 0 R W R W P...

Page 886: ...2 0 0 R W R W 23 22 PG11MD2 PG11MD2 0 0 R W R W PGn Mode 2 and 1 The combination of bits PGnMD2 and PGnMD1 controls the pin functions n 11 to 13 00 Port input 01 Port output 10 11 Reserved When set co...

Page 887: ...G2MD2 PG2MD2 0 0 R W R W 3 2 PG1MD2 PG1MD2 0 0 R W R W 1 0 PG0MD2 PG0MD2 0 0 R W R W PGn Mode 2 and 1 The combination of bits PGnMD2 and PGnMD1 controls the pin functions n 0 to 7 00 Port input other...

Page 888: ...These bits are always read as 0 The write value should always be 0 29 28 PH14MD2 PH14MD1 0 0 R W 27 26 PH13MD2 PH13MD1 0 0 R W 25 24 PH12MD2 PH12MD2 0 0 R W 23 22 PH11MD2 PH11MD2 0 0 R W 21 20 PH10MD...

Page 889: ...dable writable register that selects the pin functions PJCR is initialized to H 00000000 by a power on reset and it is not initialized by a manual reset in standby mode or in sleep mode Bit Bit Name I...

Page 890: ...PJ5MD2 PJ5MD2 0 0 R W 9 8 PJ4MD2 PJ4MD2 0 0 R W 7 6 PJ3MD2 PJ3MD2 0 0 R W 5 4 PJ2MD2 PJ2MD2 0 0 R W 3 2 PJ1MD2 PJ1MD2 0 0 R W 1 0 PJ0MD2 PJ0MD2 0 0 R W PJn Mode 2 and 1 The combination of bits PJnMD2...

Page 891: ...I O buffer Output enalbe Output data Input data Weak keeper I O buffer Figure 22 1 Internal Block Diagram of I O Buffer with Weak Keeper 22 2 2 I O Buffer with Open Drain Output PTG10 and PTG9 are mul...

Page 892: ...ction as inputs outputs when other function is selected by the port control register When the pin function shown in table 22 1 List of Multiplexed Pins is changed from port function input to other fun...

Page 893: ...ch pin is controlled by the port A control register PACR in the PFC PTA14 input output A25 output Port A PTA13 input output A24 output PTA12 input output A23 output PTA11 input output A22 output PTA10...

Page 894: ...This bit is always read as 0 The write value should always be 0 14 PA14DT 0 R W 13 PA13DT 0 R W 12 PA12DT 0 R W 11 PA11DT 0 R W 10 PA10DT 0 R W 9 PA9DT 0 R W 8 PA8DT 0 R W 7 PA7DT 0 R W 6 PA6DT 0 R W...

Page 895: ...ut does not affect pin state n 0 to 14 23 2 Port B Port B is a 9 bit input output port with the pin configuration shown in figure 23 2 Each pin is controlled by the port B control register PBCR in the...

Page 896: ...T 0 R W 3 PB3DT 0 R W 2 PB2DT 0 R W 1 PB1DT 0 R W 0 PB0DT 0 R W Bits PB8DT to PB0DT correspond to pins PTB8 to PTB0 When the pin function is general output port the value of the corresponding bit in P...

Page 897: ...t output ASEBRKAK output PTC12 input output DACK1 output PTC11 input output DACK0 output PTC10 input output DREQ1 input PTC9 input output DREQ0 input PTC8 input output TEND output PTC7 input output BA...

Page 898: ...ription 15 PC15DT 0 R W 14 PC14DT 0 R W 13 PC13DT 0 R W 12 PC12DT 0 R W 11 PC11DT 0 R W 10 PC10DT 0 R W 9 PC9DT 0 R W 8 PC8DT 0 R W 7 PC7DT 0 R W 6 PC6DT 0 R W 5 PC5DT 0 R W 4 PC4DT 0 R W 3 PC3DT 0 R...

Page 899: ...configuration shown in figure 23 4 Each pin is controlled by the port D control register PDCR in the PFC Port D PTD15 input output D31 input output PTD14 input output D30 input output PTD13 input outp...

Page 900: ...ce is set PDDR retains its previous value by a manual reset in standby mode or in sleep mode Bit Bit Name Initial Value R W Description 15 PD15DT 0 R W 14 PD14DT 0 R W 13 PD13DT 0 R W 12 PD12DT 0 R W...

Page 901: ...e 23 5 Each pin is controlled by the port E control register PECR in the PFC Port E PTE15 input output TIOC0A input output PTE14 input output TIOC0B input output PTE13 input output TIOC0C input output...

Page 902: ...eep mode Bit Bit Name Initial Value R W Description 15 PE15DT 0 R W 14 PE14DT 0 R W 13 PE13DT 0 R W 12 PE12DT 0 R W 11 PE11DT 0 R W 10 PE10DT 0 R W 9 PE9DT 0 R W 8 PE8DT 0 R W 7 PE7DT 0 R W 6 PE6DT 0...

Page 903: ...affect pin state n 0 to 15 23 6 Port F Port F is a 16 bit input port with the pin configuration shown in figure 23 6 Each pin is controlled by the port F control register PFCR in the PFC Port F PTF15...

Page 904: ...its previous value by a manual reset in standby mode or in sleep mode Bit Bit Name Initial Value R W Description 15 PF15DT 0 R W 14 PF14DT 0 R W 13 PF13DT 0 R W 12 PF12DT 0 R W 11 PF11DT 0 R W 10 PF1...

Page 905: ...value Data is written to PFDR and the value is output from the pin 1 0 Reserved 1 Other function Pin state Data is written to PFDR but does not affect pin state n 8 to 15 Table 23 7 Port F Data Regis...

Page 906: ...PGCR in the PFC Port G PTG13 input output PTG12 input output PTG11 input output PTG10 input output SDA input output PTG9 input output SCL input output PTG8 input output PTG7 input AN7 input PTG6 inpu...

Page 907: ...The write value should always be 0 13 PG13DT 0 R W 12 PG12DT 0 R W 11 PG11DT 0 R W 10 PG10DT 0 R W 9 PG9DT 0 R W 8 PG8DT 0 R W Bits PG13DT to PG8DT correspond to pins PTG13 to PTG8 When the function...

Page 908: ...R Read Write Operations PG10DT to PG9DT PGnMD2 PGnMD1 Pin State Read Write 0 0 Input Pin state Data is written to PGDR but does not affect pin state 1 Output PGDR value Data is written to PGDR and the...

Page 909: ...th the A D converter See section 22 Pin Function Controller PFC The statuses of these pins are read only when the PGDR is read but are always input to the A D converter Figure 23 8 shows the internal...

Page 910: ...output TXD2 output PTH11 input output CTS2 input output PTH10 input output SCK2 input output PTH9 input output RTS1 input output PTH8 input output RXD1 input PTH7 input output TXD1 output PTH6 input o...

Page 911: ...ed This bit is always read as 0 The write value should always be 0 14 PH14DT 0 R W 13 PH13DT 0 R W 12 PH12DT 0 R W 11 PH11DT 0 R W 10 PH10DT 0 R W 9 PH9DT 0 R W 8 PH8DT 0 R W 7 PH7DT 0 R W 6 PH6DT 0 R...

Page 912: ...bit input output port with the pin configuration shown in figure 23 10 Each pin is controlled by the port J control register PJCR in the PFC Port J PTJ12 input output AUDSYNC output PTJ11 input output...

Page 913: ...R W 6 PJ6DT 0 R W 5 PJ5DT 0 R W 4 PJ4DT 0 R W 3 PJ3DT 0 R W 2 PJ2DT 0 R W 1 PJ1DT 0 R W 0 PJ0DT 0 R W Bits PJ12DT to PJ0DT correspond to pins PTJ12 to PTJ0 When the pin function is general output por...

Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...

Page 915: ...gurations of the registers are described in the same order as the Register Addresses by functional module in order of the corresponding section numbers Reserved bits are indicated by in the bit name N...

Page 916: ...16 1 Watchdog timer control status register WTCSR 8 H A415FF86 16 2 Standby control register STBCR 8 H A415FF82 8 Standby control register 2 STBCR2 8 H A415FF88 Power down modes 8 Standby control reg...

Page 917: ...08 0062 8 Interrupt mask clear register 2 IMCR2 8 H A408 0064 8 Interrupt mask clear register 4 IMCR4 8 H A408 0068 8 Interrupt mask clear register 5 IMCR5 8 H A408 006A 8 Interrupt mask clear registe...

Page 918: ...00 BSC 32 Bus control register for area 0 CS0BCR 32 H A4FD0004 32 Bus control register for area 2 CS2BCR 32 H A4FD0008 32 Bus control register for area 3 CS3BCR 32 H A4FD000C 32 Bus control register f...

Page 919: ...01 0034 16 32 DMA transfer count register_1 DMATCR_1 32 H A401 0038 16 32 DMA channel control register _1 CHCR_1 32 H A401 003C 8 16 32 DMA source address register_2 SAR_2 32 H A401 0040 16 32 DMA des...

Page 920: ...4A 0008 16 Compare match timer constant register_0 CMCOR_0 16 H A44A 000C 16 Compare match timer start register_1 CMSTR_1 16 H A44B 0000 16 Compare match timer control status register_1 CMCSR_1 16 H A...

Page 921: ...r C_3 TGRC_3 16 H A449 0024 16 32 Timer general register D_3 TGRD_3 16 H A449 0026 16 32 Timer general register C_4 TGRC_4 16 H A449 0028 16 32 Timer general register D_4 TGRD_4 16 H A449 002A 16 32 T...

Page 922: ...le register_2 TIER_2 8 H A449 00A4 8 16 32 Timer status register_2 TSR_2 8 H A449 00A5 8 16 32 Timer counter_2 TCNT_2 16 H A449 00A6 16 32 Timer general register A_2 TGRA_2 16 H A449 00A8 16 32 Timer...

Page 923: ...ta register_2 SCFTDR_2 8 H A442 000C 8 Serial status register_2 SCFSR_2 16 H A442 0010 16 Receive FIFO data register_2 SCFRDR_2 8 H A442 0014 8 FIFO control register_2 SCFCR_2 16 H A442 0018 16 FIFO d...

Page 924: ...D0 data register A ADDRA0 16 H A44E 0000 ADC 16 A D0 data register B ADDRB0 16 H A44E 0002 16 A D0 data register C ADDRC0 16 H A44E 0004 16 A D0 data register D ADDRD0 16 H A44E 0006 16 A D1 data regi...

Page 925: ...43 0032 8 16 Port H data register PHDR 16 H A443 0034 8 16 Port J data register PJDR 16 H A443 0036 8 16 Notes 1 This register only accepts 16 bit writing to prevent incorrect writing In this case the...

Page 926: ...31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module FRQCR CKOEN STC1 STC0 CPG IFC1 IFC0 PFC1 PFC0 WTCNT WDT WTCSR TME WT IT RSTS W...

Page 927: ...R8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IMR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 IMR1 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 IMR2 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 IMR4 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 IMR5 IM7...

Page 928: ...2 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPRE IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9 IPR8 IPR7 IPR6 IPR5 IPR4 IPR3 IPR2 IPR1 IPR0 IPRJ IPR15 IPR14 IPR13 IPR12 IPR11 IPR10 IPR9...

Page 929: ...MB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 BBRB XYE XYS CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0 BRSR SVF BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BS...

Page 930: ...W2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS3BCR IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 IWRRD2 IWRR...

Page 931: ...CR IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 BSC IWRWS1 IWRWS0 IWRRD2 IWRRD1 IWRRD0 IWRRS2 IWRRS1 IWRRS0 TYPE2 TYPE1 TYPE0 BSZ1 BSZ0 CS6BBCR IWW2 IWW1 IWW0 IWRWD2 IWRWD1 IWRWD0 IWRWS2 IWRWS1 IWRWS0 I...

Page 932: ...24 16 8 0 Module CS3WCR 1 BSC BAS WR3 WR2 WR1 WR0 WM CS3WCR 4 WTRP1 WTRP0 WTRCD1 WTRCD0 A3CL1 A3CL0 TRWL1 TRWL0 WTRC1 WTRC0 CS4WCR 1 BAS WW2 WW1 WW0 SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 CS4WCR 2 BEN BW...

Page 933: ...28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module CS6BWCR 1 BSC BAS SW1 SW0 WR3 WR2 WR1 WR0 WM HW1 HW0 CS6BWCR 5 MPXAW1 MPXAW0 MPXMD BW1 BW0 W3 W2 W1 W0 WM SDCR A2ROW1 A2ROW...

Page 934: ...15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module DMATCR_0 DMAC CHCR_0 TC DO TL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 DL DS TB TS1 TS0...

Page 935: ...iation Bit 31 23 15 7 Bit 30 22 14 6 Bit 29 21 13 5 Bit 28 20 12 4 Bit 27 19 11 3 Bit 26 18 10 2 Bit 25 17 9 1 Bit 24 16 8 0 Module DAR_2 DMAC DMATCR_2 CHCR_2 TC DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TB TS1...

Page 936: ...MID0 C3RID1 C3RID0 C2MID5 C2MID4 C2MID3 C2MID2 C2MID1 C2MID0 C2RID1 C2RID0 SDIR T17 T16 T15 T14 T13 T12 T11 T10 H UDI SDIDH DID31 DID30 DID29 DID28 DID27 DID26 DID25 DID24 DID23 DID22 DID21 DID20 DID1...

Page 937: ...TPSC1 TPSC0 MTU TCR_4 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_3 BFB BFA MD3 MD2 MD1 MD0 TMDR_4 BFB BFA MD3 MD2 MD1 MD0 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IO...

Page 938: ...RB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TCFD TCFV TGFD TGFC TGFB TGFA TSR_4 TCFD TCFV TGFD TGFC TGFB TGFA TSTR CST4 CST3 CST2 CST1 CST0 TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 TCR_0 CCLR2 CCLR1 C...

Page 939: ...C_0 TGRD_0 TCR_1 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_1 MD3 MD2 MD1 MD0 TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_1 TTGE TGFASEL TCIEU TCIEV TGIEB TGIEA TSR_1 TCFD TCFU TCFV...

Page 940: ..._0 SCIF C A CHR PE O E STOP CKS1 CKS0 SCBRR_0 SCSCR_0 TIE RIE TE RE REIE CKE1 CKE0 SCFTDR_0 SCFSR_0 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 ER TEND TDFE BRK FER PER RDF DR SCFRDR_0 SCFCR_0 RSTRG2 RSTR...

Page 941: ...C A CHR PE O E STOP CKS1 CKS0 SCBRR_2 SCSCR_2 TIE RIE TE RE REIE CKE1 CKE0 SCFTDR_2 SCFSR_2 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 ER TEND TDFE BRK FER PER RDF DR SCFRDR_2 SCFCR2 RSTRG2 RSTRG1 RSTRG0...

Page 942: ...EP0iDE USBISR0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR EP0iTS USBEPSTL ASCE EP3STL EP2STL EP1STL EP0STL USBIER0 BRST EP1FULL EP2TR EP2EMPTY SETUPTS EP0oTS EP0iTR EP0iTS USBIER1 EP3TR EP3TS V...

Page 943: ...D2 PB7MD1 PB6MD2 PB6MD1 PB5MD2 PB5MD1 PB4MD2 PB4MD1 PB3MD2 PB3MD1 PB2MD2 PB2MD1 PB1MD2 PB1MD1 PB0MD2 PB0MD1 PCCR PC15MD2 PC15MD1 PC14MD2 PC14MD1 PC13MD2 PC13MD1 PC12MD2 PC12MD1 PC11MD2 PC11MD1 PC10MD2...

Page 944: ...0MD1 PH9MD2 PH9MD1 PH8MD2 PH8MD1 PH7MD2 PH7MD1 PH6MD2 PH6MD1 PH5MD2 PH5MD1 PH4MD2 PH4MD1 PH3MD2 PH3MD1 PH2MD2 PH2MD1 PH1MD2 PH1MD1 PH0MD2 PH0MD1 PJCR PJ12MD2 PJ12MD1 PJ11MD2 PJ11MD1 PJ10MD2 PJ10MD1 PJ...

Page 945: ...PF0DT PGDR PG13DT PG12DT PG11DT PG10DT PG9DT PG8DT PG7DT PG6DT PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT PHDR PH14DT PH13DT PH12DT PH11DT PH10DT PH9DT PH8DT PH7DT PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT...

Page 946: ...etained Retained INTEVT2 Initialized Initialized Retained Retained Retained TRA Initialized Initialized Retained Retained Retained Exception handling EXPEVT Initialized Initialized Retained Retained R...

Page 947: ...CR1 Initialized Initialized Retained Retained ICR3 Initialized Initialized Retained Retained IPRC Initialized Initialized Retained Retained IPRD Initialized Initialized Retained Retained IPRE Initiali...

Page 948: ...etained Retained CS0WCR Initialized Retained Retained Retained CS2WCR Initialized Retained Retained Retained CS3WCR Initialized Retained Retained Retained CS4WCR Initialized Retained Retained Retained...

Page 949: ...R Initialized Initialized Retained Retained Retained DMARS0 Initialized Initialized Retained Retained Retained DMARS1 Initialized Initialized Retained Retained Retained SDIR Initialized 4 Retained Ret...

Page 950: ...Initialized Initialized Retained TIORL_4 Initialized Retained Initialized Initialized Retained TIER_3 Initialized Retained Initialized Initialized Retained TIER_4 Initialized Retained Initialized Ini...

Page 951: ...ined Initialized Initialized Retained TSR_0 Initialized Retained Initialized Initialized Retained TCNT_0 Initialized Retained Initialized Initialized Retained TGRA_0 Initialized Retained Initialized I...

Page 952: ...tained SCFSR_0 Initialized Retained Retained Retained Retained SCFRDR_0 Undefined Retained Retained Retained Retained SCFCR_0 Initialized Retained Retained Retained Retained SCFDR_0 Initialized Retain...

Page 953: ...DR0o Undefined Retained Retained Retained Retained USBTRG Initialized Retained Retained Retained Retained USBFCLR Initialized Retained Retained Retained Retained USBEPSZ0o Initialized Retained Retaine...

Page 954: ...Retained Initialized Initialized Retained ADCSR0 Initialized Retained Initialized Initialized Retained ADCSR1 Initialized Retained Initialized Initialized Retained ADCR Initialized Retained Initializ...

Page 955: ...FDR Initialized Retained Retained Retained PORT PGDR Initialized 3 Retained Retained Retained PHDR Initialized Retained Retained Retained PJDR Initialized Retained Retained Retained Notes 1 Not initia...

Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...

Page 957: ...s Table 25 1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage I O VCC Q 0 3 to 3 8 V Power supply voltage Internal VCC VCC PLL1 VCC PLL2 0 3 to 2 1 V Input voltage other than ports...

Page 958: ...values for the power on procedure are shown below VCCQ min voltage VCCQ 3 3 V system power supply VCC 1 8 V system power supply VCC min voltage tpwu tunc GND VCC 2 level voltage The time at which Vcc...

Page 959: ...ion 3 The negative values in the maximum permissible value column indicate the allowed difference in the time the voltages supplied as VccQ and Vcc take to rise Therefore these figures do not allow th...

Page 960: ...current All input pins Iin 1 0 A Vin 0 5 to VCCQ 0 5 V Three state leakage current All input output pins all output pins except for pins with weak keeper off state ISTI 1 0 A Vin 0 5 to VCCQ 0 5 V In...

Page 961: ...p Max Unit Test Conditions VCCQ 3 0 3 3 3 6 Power supply VCC VCC PLL1 VCC PLL2 1 71 1 8 1 89 V Input high voltage RESETP RESETM NMI MD3 MD2 MD0 ASEMD0 TRST VCCQ 0 9 VCCQ 0 3 EXTAL CKIO VCCQ 0 3 VCCQ 0...

Page 962: ...CK2 RxD0 to RxD2 CTS0 to CTS2 IRQ7 to IRQ0 VT VT VCCQ 0 05 V 2 4 IOH 200 A Output high voltage All output pins VOH 2 0 V IOH 2 mA PE0 to PE4 PE6 1 5 IOL 15 mA Output low voltage All pins except for ab...

Page 963: ...A pins open drain pins When the port functions are selected as the general inputs or outputs however these pins have the usual VOH VOL and VIH VIL characteristics Table 25 3 DC Characteristics 4 USB R...

Page 964: ...Output low voltage VOL 0 3 V Tri state leak current ILO 10 10 A 0 V VIN 3 3 V Note The DP and DM pins Table 25 4 Permissible Output Currents Conditions VCC 1 8 V 5 VCC Q 3 0 V to 3 6 V AVCC 3 0 V to 3...

Page 965: ...handled as signals in synchronization with a clock The setup and hold times for input pins must be followed Table 25 5 Maximum Operating Frequency Conditions VCC Q 3 0 V to 3 6 V VCC 1 8 V 5 AVCC 3 0...

Page 966: ...z CKIO clock input cycle time tCKcyc 20 50 ns CKIO clock input low pulse width tCKIL 7 ns CKIO clock input high pulse width tCKIH 7 ns CKIO clock input rising time tCKIr 3 ns CKIO clock input falling...

Page 967: ...VIL VIL EXTAL input Note When the clock is input on the EXTAL pin Figure 25 2 EXTAL Clock Input Timing tCKIH tCKIF tCKIR tCKIL tCKIcyc VIH VIH VIH 1 2 VCCQ 1 2 VCCQ VIL VIL CKIO input Figure 25 3 CKIO...

Page 968: ...nternal oscillator is used Oscillation settling time Figure 25 5 Oscillation Settling Timing Power On CKIO CKIO2 tphckio2 Figure 25 6 Phase Difference between CKIO and CKIO2 CKIO Internal clock Oscill...

Page 969: ...005 Page 919 of 982 REJ09B0023 0400 CKIO Internal clock Oscillation settling time Standby period Note Oscillation settling time when the internal oscillator is used tOSC3 NMI IRQ Figure 25 8 Oscillati...

Page 970: ...to IRQ0 setup time 1 tIRQS 30 ns IRQ7 to IRQ0 hold time tIRQH 30 ns BACK delay time tBACKD 1 2tcyc 13 ns 25 11 25 12 STATUS1 STATUS0 delay time tSTD 100 ns Bus tri state delay time 1 tBOFF1 0 100 ns B...

Page 971: ...005 Page 921 of 982 REJ09B0023 0400 CKIO tRESPS MS tRESPS MS RESETP RESETM tRESPW MW Figure 25 9 Reset Input Timing CKIO RESETP RESETM tRESPH MH tRESPS MS VIH VIL NMI tNMIH tNMIS VIH VIL IRQ7 to IRQ0...

Page 972: ...CKIO HIZCNT 0 BREQH t BOFF2 t BREQS t BACKD t BACKD t BREQH t BREQS t BON1 t BOFF1 t BOFF2 t BON2 t BON2 t When HZCNT 1 When HZCNT 0 Figure 25 11 Bus Release Timing CKIO input tSTD tBOFF2 tBOFF1 tSTD...

Page 973: ...time 2 tCSD2 1 2tcyc 1 2tcyc 12 ns 25 40 25 41 Read write delay time 1 tRWD1 1 12 ns 25 13 to 25 39 Read write delay time 2 tRWD2 1 2tcyc 1 2tcyc 12 ns 25 40 25 41 Read strobe delay time tRSD 1 2tcyc...

Page 974: ...hold time 2 tWTH2 4 ns 25 16 RAS delay time 1 tRASD1 1 12 ns 25 23 to 25 34 25 36 to 25 39 RAS delay time 2 tRASD2 1 2tcyc 1 2tcyc 12 ns 25 40 25 41 CAS delay time 1 tCASD1 1 12 ns 25 23 to 25 39 CAS...

Page 975: ...iming T1 tAD1 tAS tCSD1 T2 tAD1 tRWD1 tRWD1 tCSD1 tRSD tRSD tAH tRDH1 tRDS1 tWED1 tWED1 tAH tBSD tBSD tDACD tDACD tWDH1 tWDD1 CKIO A25 to A0 CSn RD WR RD D31 to D0 Read WEn BS DACKn Note Waveform for...

Page 976: ...Tw T2 tAD1 tRWD1 tRWD1 tCSD1 tRSD tRSD tAH tRDH1 tRDS1 tWED1 tWED1 tAH tBSD tBSD tWTH1 tWTS1 tDACD tDACD tWDH1 tWDD1 WAIT Note Waveform for DACKn when active low is selected CKIO A25 to A0 CSn RD WR R...

Page 977: ...tRWD1 tCSD1 tRSD tRSD tAH tRDH1 tRDS1 tWED1 tWED1 tAH tBSD tBSD tWTH1 tWTS1 tWTH1 tWTS1 tDACD tDACD tWDH1 tWDD1 WAIT Note Waveform for DACKn when active low is selected CKIO A25 to A0 CSn RD WR RD D31...

Page 978: ...tRWD1 tCSD1 tRSD tRSD tAH tRDH1 tRDS1 tWED1 tWED1 tAH tBSD tBSD tWTH2 tWTS2 tWTH2 tWTS2 tDACD tDACD tWDH1 tWDD1 WAIT Note Waveform for DACKn when active low is selected CKIO A25 to A0 CSn RD WR RD D31...

Page 979: ...tWDH1 tWDH1 tWDD1 tBSD tBSD tDACD tDACD tDACD tDACD tBSD tBSD tRWD1 tRWD1 tRWD1 tCSD1 tCSD1 tCSD1 tAS tAD1 tAD1 Tw T2 Taw T1 Tw T2 Taw tWTH1 tWTS1 tWTH1 tWTS1 WAIT Note Waveform for DACKn when active...

Page 980: ...1 Data Data tBSD tBSD tWTH1 tWTS1 tAHD tAHD tWTH1 tWTS1 tDACD tDACD Address tWDH1 tWDD1 tMAD CKIO A25 to A0 CS5B RD WR RD AH D15 to D0 Read WE1 to WE0 BS WAIT DACKn D15 to D0 Write Address tMAH tMAD t...

Page 981: ...tFMD tRWD1 tCSD1 CKIO A25 to A0 CS6B RD WR D31 to D0 D31 to D0 Read BS FRAME WAIT WEn RD Write tWDH1 tWDD1 tRDS2 tWDD1 tBSD tDACD tDACD tWTH1 tWTS1 tBSD tWDH1 tWDH1 tRDH2 Note Waveform for DACKn and T...

Page 982: ...tBSD tWDH1 tRDH1 tAD1 tCSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 Read RD WR RD WR BS WAIT Write tDACD tDACD tBSD tWTS1 tWTS1 tRWD1 tRWD1 tRWD1 tWED1 tWED1 tWTH1 tWTH1 DACKn TENDn Note Wavefo...

Page 983: ...tWDH1 tRDH1 tAD1 tCSD1 CKIO A25 to A0 CSn WEn RD D31 to D0 D31 to D0 Read RD WR RD WR BS WAIT DACKn TENDn Note Waveform for DACKn and TENDn when active low is selected Write tDACD tDACD tBSD tWTS1 tWT...

Page 984: ...Tw Twx T2B Twb T2B tAD2 tAD2 tCSD1 CKIO A25 to A0 CSn RD WR D31 to D0 WEn BS RD WAIT Note Waveform for DACKn and TENDn when active low is selected DACKn TENDn tAD1 tBSD tDACD tDACD tBSD tRWD1 tWTS1 t...

Page 985: ...CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address ReadA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 Note 1 An...

Page 986: ...o A0 CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address ReadA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 Note 1 An address pi...

Page 987: ...RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address ReadA command Read command Column address 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tR...

Page 988: ...Sn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address Read command Column address 1 to 4 tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tRDH2 tRDS2 ReadA co...

Page 989: ...CSn RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WriteA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 Note 1 An a...

Page 990: ...n RD WR A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WriteA command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 Note 1 An addr...

Page 991: ...12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WriteA command WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 tWDH2 tWDD...

Page 992: ...A12 A11 1 D31 to D0 tRASD1 tRASD1 RASU L Row address WriteA command WRIT command Column address tCASD1 tCASD1 CASU L tBSD tBSD High BS CKE tDQMD1 tDQMD1 DQMxx tDACD tDACD DACKn 2 tWDH2 tWDD2 tWDH2 tW...

Page 993: ...Read command Column address tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD tRDH2 tRDS2 tRDH2 tRDS2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An add...

Page 994: ...tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD tRDH2 tRDS2 tRDH2 tRDS2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An address pin to be connected to...

Page 995: ...nd Column address Row address tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD tRDH2 tRDS2 tRDH2 tRDS2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An a...

Page 996: ...of SDRAM 2 Waveform for DACKn when active low is selected Tc2 Tc3 Tc4 Tr Tc1 tAD1 tCSD1 tAD1 tAD1 tAD1 tAD1 tAD1 tRWD1 tRWD1 tRWD1 tCSD1 tAD1 tAD1 tAD1 tRASD1 tRASD1 Row address Write command Column...

Page 997: ...tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD tWDH2 tWDD2 tWDH2 tWDD2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An address pin to be connected to...

Page 998: ...1 tAD1 Column address tCASD1 tCASD1 tBSD tBSD High tDQMD1 tDQMD1 tDACD tDACD tWDH2 tWDD2 tWDH2 tWDD2 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An address p...

Page 999: ...tRASD1 tRASD1 tAD1 tAD1 tCASD1 tCASD1 High Hi Z 3 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An address pin to be connected to pin A10 of SDRAM 2 Waveform f...

Page 1000: ...SD1 tRASD1 tRASD1 tAD1 tAD1 tCASD1 tCASD1 Hi Z 3 tCKED1 tCKED1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Note 1 An address pin to be connected to pin A10 of SDRAM...

Page 1001: ...AD1 tCASD1 tCASD1 Hi Z 3 tCSD1 tCSD1 tRASD1 tRASD1 tCASD1 tCASD1 tCSD1 tCSD1 tRWD1 tRWD1 tRASD1 tRASD1 tCASD1 tCASD1 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn 2 Not...

Page 1002: ...AD3 tAD3 tAD3 tCSD2 tRWD2 tRWD2 tRWD2 tCASD2 tCASD2 tCASD2 tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tRASD2 tBSD tBSD tBSD tBSD tDQMD2 tDQMD2 tDQMD2 tDQMD2 tRDS4 tRDH4 tWDD3 tWDH3 tCSD2 tCSD2 tCSD2 tDACD tDA...

Page 1003: ...D2 tRASD2 tRASD2 tRWD2 tRWD2 tRASD2 tAD3 tAD3 CKIO A25 to A0 CSn RD WR A12 A11 1 D31 to D0 RASU L CASU L BS CKE DQMxx DACKn TENDn 2 Note 1 An address pin to be connected to pin A10 of SDRAM 2 Waveform...

Page 1004: ...ising time tSCKR 1 5 tPcyc 25 42 Input clock falling time tSCKF 1 5 tPcyc 25 42 Input clock width tSCKW 0 4 0 6 tScyc 25 42 Transmit data delay time synchronous tTXD 3 tPcyc 15 ns 25 43 Receive data s...

Page 1005: ...a transmission RxD data reception tRXH tRXS Figure 25 43 SCIF Input Output Timing in Synchronous Mode tPORTS CKIO Ports 7 to 0 read Ports 7 to 0 write tPORTH tPORTD Figure 25 44 I O Port Timing tDRQS...

Page 1006: ...m Symbol Min Max Unit Figure s Output compare output delay time tTOCD Bcyc 2 20 ns 25 47 Input capture input setup time tTICS Bcyc 2 20 ns Timer input setup time tTCKS Bcyc 2 20 ns 25 48 Timer clock p...

Page 1007: ...al Timing Table 25 11 Output Enable POE Timing Conditions VCC 1 8 V 5 VCC Q AVCC 3 0 V to 3 6 V VSS VSS Q AVSS 0 V Ta 40 C to 85 C Item Symbol Min Max Unit Figure s POE input setup time tPOES Bcyc 2 1...

Page 1008: ...yc 300 ns SCL SDA input rising time tSR 300 ns SCL SDA input falling time tSF 300 ns SCL SDA input spike pulse removal time 2 tSP 1 2 tPcyc 1 SDA input bus free time tBUF 5 tPcyc tPcyc Start condition...

Page 1009: ...05 Page 959 of 982 REJ09B0023 0400 SCL VIH VIL tSTAH tBUF P S tSF tSR tSCL tSDAH tSCLH tSCLL SDA Sr tSTAS tSP tSTOS tSDAS P Legend S Start condition P Stop condition Sr Start condition for retransmiss...

Page 1010: ...25 51 TCK high pulse width tTCKH 0 4 0 6 tTckcyc TCK low pulse width tTCKL 0 4 0 6 tTckcyc TRST setup time tTRSTS 20 ns 25 52 TRST hold time tTRSTH 50 tcyc TDI setup time tTDIS 10 ns 25 53 TDI hold ti...

Page 1011: ...ure 25 52 TRST Input Timing Reset Hold State TCK TMS TDI TDO When boundary scan is not performed When boundary scan is performed tTDIS tTDIH tTCKcyc tTMSS tTMSH tTDOD tTDOD Figure 25 53 H UDI Data Tra...

Page 1012: ...lock Timing Conditions VCC 1 8 V 5 VCC Q 3 0 V to 3 6 V AVCC 3 0 V to 3 6 V VSS VSS Q AVSS 0 V Ta 40 C to 85 C Item Symbol Min Max Unit Figure s Frequency 48 MHz tFREQ 47 9 48 1 MHz 25 55 Clock rising...

Page 1013: ...CL 50pF Rising falling time ratio tR tF 90 110 Output crossover voltage VCRS 1 3 2 0 V CL 50pF Output driver resistance ZDRU 28 44 Notes 1 Transceivers conform to the full speed specification 2 The r...

Page 1014: ...V where RESETP RESETM ASEMD0 NMI TRST EXTAL CKIO TCK MD0 MD2 MD3 and Schmitt inputs are within VSS Q to VCC Q Input rising and falling times 1 ns IOL IOH CL VREF LSI output pin DUT output Notes CL is...

Page 1015: ...2 7 V to 3 6 V VSS Q VSS AVSS 0 V Ta 40 C to 85 C Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 10 5 s Analog input capacitance 20 1 pF Permissible signal source impedance single sour...

Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...

Page 1017: ...by Sleep Bus Released Reset Clock EXTAL clock modes 2 and 6 I I I I I EXTAL clock mode 7 Z 1 Z 1 Z 1 Z 1 Z 1 EXTAL clock modes 2 and 6 O O O O O EXTAL clock mode 7 O 1 O 1 O 1 O 1 O 1 EXTAL clock mode...

Page 1018: ...Z H 3 O Z BS H O Z H 3 O Z CAS U L RAS U L Z O O Z 2 O O Z 2 6 WE0 DQMLL WE1 DQMLU WE2 DQMUL WE3 DQMUU AH H O Z H 3 O Z RD WR RD H O Z H 3 O Z CKE Z O O Z 2 O O Z 2 6 WAIT Z I Z I Z FRAME Z O Z H 3 O...

Page 1019: ...I O RTS 2 0 Z I O K Z 4 I O I O CTS 2 0 Z I O K Z 4 I O I O AUD AUDSYNC Z O O O O AUDCK O O O O O AUDATA 3 0 Z O O O O H UDI 8 ASEBRKAK O O O O O ASEMD0 I I 5 I 5 I 5 I 5 TCK I I I I I TDI I I I I I...

Page 1020: ...common control register of the BSC 3 Controlled by the HIZMEM bit in the common control register of the BSC 4 Controlled by the HIZ bit in the standby control register 5 The pin must not be open since...

Page 1021: ...4 12 0 Z I O Z K I O I O PTC 13 O I O Z K I O I O PTD 15 0 Z I O Z K I O I O PTE 15 0 Z I O Z K I O I O PTF 15 0 Z I O Z K I O I O PTG 13 11 8 Z I O Z K I O I O PTG 10 9 Z I O Z K I O I O PTG 7 0 Z I...

Page 1022: ...5 Page 972 of 982 REJ09B0023 0400 B Product Lineup Product Model Package Code SH7641 HD6417641BP100 100 MHz version P LFBGA1717 256 Note For details of packages please contact your nearest Renesas Tec...

Page 1023: ...e JEDEC JEITA P LFBGA 1717 256 0 35 to 0 45 0 20 0 15 C C 0 15 4 C 1 40 Max 0 08 0 15 0 44 to 0 64 256 M C M C A B 0 80 B A A1 CORNER 20 19 A B C D E F G H J K L M N P R T U V W Y 18 17 16 15 14 13 12...

Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...

Page 1025: ...added Section 9 Exception Handling 9 5 Note on Initializing this LSI 217 MOV W H FF40 R10 MOV L H A4FC0000 R8 MOV H 10 R9 MOV B R10 R10 MOV B R10 R10 MOV B R10 R10 MOV L R9 R8 MOV L H FC000000 R1 MOV...

Page 1026: ...38 Synchronous DRAM Self Refreshing Timing WTRP 1 Cycle Figure 25 39 Synchronous DRAM Mode Register Write Timing WTRP 1 Cycle Figure 25 41 Synchronous DRAM Self Refreshing Timing in Low Frequency Mod...

Page 1027: ...urst mode 438 Burst MPX I O interface 382 Burst ROM interface 376 386 Burst ROM Read Cycle 934 Bus arbitration 399 Bus Cycle of Byte Selection SRAM 932 Bus state controller 146 Bus State Controller 26...

Page 1028: ...state 673 I I O buffer with open drain output 841 I O buffer with weak keeper 841 I O ports 843 I2 C Bus Format 488 I2 C bus interface 2 473 Illegal general instruction exception 207 Illegal slot inst...

Page 1029: ...eriodic counter 562 Phase counting mode 581 Pin function controller 819 PLL circuit 1 145 PLL circuit 2 145 Power down modes 163 Power on reset 164 Power On Sequence 908 Priority 202 235 Procedure reg...

Page 1030: ...54 PGCR 836 PGDR 857 PHCR 838 PHDR 861 PJCR 839 PJDR 863 RTCNT 319 RTCOR 319 RTCSR 317 RWTCNT 320 SAR DMAC 409 SAR IIC2 486 SCBRR 707 SCFCR 714 SCFDR 717 SCFRDR 690 SCFSR 699 SCFTDR 691 SCLSR 720 SCRS...

Page 1031: ...O 685 Shadow area 274 Shift instructions 76 Shift operations 109 Single address mode 434 Single data addressing 53 Single mode 805 Slave address 489 Sleep mode 163 171 Software standby mode 163 Stall...

Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...

Page 1033: ...e Rev 1 00 Sep 19 2003 Rev 4 00 Sep 14 2005 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions...

Page 1034: ...688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd Unit2607 Ruijing Bui...

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Page 1036: ...SH7641 Hardware Manual...

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