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Section 2 CPU
Rev. 4.00 Sep. 14, 2005 Page 90 of 982
REJ09B0023-0400
Table 2.31 DSP Operation Instructions
Instruction
Instruction Code
Operation
Execution
States
DC
PMULS Se,Sf,Dg 111110
**********
0100eeff0000gg00
Se
*
Sf
→
Dg (signed)
1
PADD
Sx,Sy,Du
PMULS
Se,Sf,Dg
111110
**********
0111eeffxxyygguu
Sx + Sy
→
Du
Se
*
Sf
→
Dg (signed)
1
*
PSUB
Sx,Sy,Du
PMULS
Se,Sf,Dg
111110
**********
0110eeffxxyygguu
Sy – Sy
→
Du
Se
*
Sf
→
Dg (signed)
1
*
PADD
Sx,Sy,Dz
111110
**********
10110001xxyyzzzz
Sx + Sy
→
Dz 1
*
DCT PADD
Sx,Sy,Dz 111110
**********
10110010xxyyzzzz
If DC = 1, Sx + Sy
→
Dz
If DC = 0, nop
1
DCF PADD
Sx,Sy,Dz 111110
**********
10110011xxyyzzzz
If DC = 0, Sx + Sy
→
Dz
If DC = 1, nop
1
PSUB
Sx,Sy,Dz
111110
**********
10100001xxyyzzzz
Sx – Sy
→
Dz 1
*
DCT PSUB
Sx,Sy,Dz 111110
**********
10100010xxyyzzzz
If DC = 1, Sx – Sy
→
Dz
If DC = 0, nop
1
DCF PSUB
Sx,Sy,Dz 111110
**********
10100011xxyyzzzz
If DC = 0, Sx – Sy
→
Dz
If DC = 1, nop
1
PSHA
Sx,Sy,Dz
111110
**********
10010001xxyyzzzz
If Sy > = 0, Sx << Sy
→
Dz
(arithmetic shift)
If Sy<0, Sx>>Sy
→
Dz
1
*
DCT PSHA
Sx,Sy,Dz 111110
**********
10010010xxyyzzzz
If DC = 1 & Sy > = 0,
Sx << Sy
→
Dz (arithmetic
shift)
If DC = 1 & Sy < 0,
Sx >> Sy
→
Dz
If DC = 0, nop
1
Summary of Contents for HD6417641
Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...
Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...
Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...
Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...
Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
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Page 1036: ...SH7641 Hardware Manual...