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Section 11 User Break Controller (UBC)
Rev. 4.00 Sep. 14, 2005 Page 246 of 982
REJ09B0023-0400
11.2.4 Break
Address Register B (BARB)
BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition
in channel B. Control bits CDB1, CDB0, XYE, and XYS in BBRB select one of the four address
buses for break condition B.
Bit Bit
Name
Initial
Value R/W Description
31 to 0
BAB31 to
BAB0
All 0
R/W
Break Address B
Store an address which specifies a break condition in
channel B.
If the I bus or L bus is selected in BBRB, an IAB or
LAB address is set in BAB31 to BAB0.
If the X memory is selected in BBRB, the values in
bits 15 to 1 in XAB are set in BAB31 to BAB17. In this
case, the values in BAB16 to BAB0 are arbitrary.
If the Y memory is selected in BBRB, the values in
bits 15 to 1 in YAB are set in BAB15 to BAB1. In this
case, the values in BAB31 to BAB16 are arbitrary.
Table 11.1 Specifying Break Address Register
Bus Selection in
BBRB
BAB31 to BAB17
BAB16
BAB15 to BAB1
BAB0
L bus
LAB31 to LAB0
I bus
IAB31 to IAB0
X bus
XAB15 to XAB1
Don't care
Don't care
Don't care
Y bus
Don't care
Don't care
YAB15 to YAB1
Don't care
Summary of Contents for HD6417641
Page 2: ...Rev 4 00 Sep 14 2005 Page ii of l...
Page 7: ...Rev 4 00 Sep 14 2005 Page vii of l...
Page 11: ...Rev 4 00 Sep 14 2005 Page xi of l USB Universal serial bus WDT Watch dog timer...
Page 12: ...Rev 4 00 Sep 14 2005 Page xii of l...
Page 28: ...Rev 4 00 Sep 14 2005 Page xxviii of l...
Page 204: ...Section 4 Clock Pulse Generator CPG Rev 4 00 Sep 14 2005 Page 154 of 982 REJ09B0023 0400...
Page 212: ...Section 5 Watchdog Timer WDT Rev 4 00 Sep 14 2005 Page 162 of 982 REJ09B0023 0400...
Page 228: ...Section 6 Power Down Modes Rev 4 00 Sep 14 2005 Page 178 of 982 REJ09B0023 0400...
Page 246: ...Section 8 X Y Memory Rev 4 00 Sep 14 2005 Page 196 of 982 REJ09B0023 0400...
Page 318: ...Section 11 User Break Controller UBC Rev 4 00 Sep 14 2005 Page 268 of 982 REJ09B0023 0400...
Page 454: ...Section 12 Bus State Controller BSC Rev 4 00 Sep 14 2005 Page 404 of 982 REJ09B0023 0400...
Page 504: ...Section 14 U Memory Rev 4 00 Sep 14 2005 Page 454 of 982 REJ09B0023 0400...
Page 566: ...Section 17 Compare Match Timer CMT Rev 4 00 Sep 14 2005 Page 516 of 982 REJ09B0023 0400...
Page 868: ...Section 21 A D Converter Rev 4 00 Sep 14 2005 Page 818 of 982 REJ09B0023 0400...
Page 914: ...Section 23 I O Ports Rev 4 00 Sep 14 2005 Page 864 of 982 REJ09B0023 0400...
Page 956: ...Section 24 List of Registers Rev 4 00 Sep 14 2005 Page 906 of 982 REJ09B0023 0400...
Page 1016: ...Section 25 Electrical Characteristics Rev 4 00 Sep 14 2005 Page 966 of 982 REJ09B0023 0400...
Page 1024: ...Appendix Rev 4 00 Sep 14 2005 Page 974 of 982 REJ09B0023 0400...
Page 1032: ...Rev 4 00 Sep 14 2005 Page 982 of 982 REJ09B0023 0400 X X Y data addressing 52 X Y memory 193...
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