System Register Block
UG0331 User Guide Revision 15.0
731
22.3.98 MSS Internal Status Register
22.3.99 MSS External Status Register
Table 756 •
MSS_INTERNAL_SR
Bit
Number Name
Reset
Value
Description
[31:7]
Reserved
0
6
DDR_FIC_INT
0
Indicates an interrupt from DDR_FIC.
5
MDDR_ECC_INT
0
Indicates when an SECDED interrupt from the MDDR
subsystem is asserted.
4
MDDR_IO_CALIB_INT
0
Interrupt is generated when the MDDR calibration is finished.
3
FAB_PLL_LOCKLOST_INT 0
Indicates that a falling edge event occurred on the
FAB_PLL_LOCK signal. This indicates that the fabric PLL lost
lock.
2
FAB_PLL_LOCK_INT
0
Indicates that a rising edge event occurred on the
FAB_PLL_LOCK signal. This indicates that the fabric PLL came
into lock.
1
MPLL_LOCKLOST_INT
0
Indicates that a falling edge event occurred on the MPLL_LOCK
signal. This indicates that the MPLL lost lock.
0
MPLL_LOCK_INT
0
Indicates that a rising edge event occurred on the MPLL_LOCK
signal. This indicates that the MPLL came into lock.
Table 757 •
MSS_EXTERNAL_SR
Bit
Number Name
Reset
Value
Description
[31:19]
Reserved
0
18
CC_HRESP_ERR
Indicates whether any accesses to the corresponding master on the
CACHE resulted in HRESP assertion by the slave to the CACHE (and
hence to the master) or HRESP generated by the CACHE itself to the
master (in the case of an invalid address being accessed). The
CACHE does pass the HRESP signal through to the requesting
master, but the event is also registered in this register. The bit
definitions are as follows:
Bit 0: Corresponds to an HRESP assertion being issued to the DCode
bus master.
Bit 1: Corresponds to an HRESP assertion being issued to the ICode
bus master.
Bit 2: Corresponds to an HRESP assertion being issued to the SBus
master.
17
DDRB_LOCK_MID
0
Indicates which master (AHB bus or HPDMA) is responsible for lock
timeout condition.
0: AHB bus master
1: HPDMA