System Register Block
UG0331 User Guide Revision 15.0
732
16
DDRB_LCKOUT
0
Asserted when lock timeout counter reaches its maximum value. Lock
time out counter (20-bit) is maintained in the MSS DDR bridge, which
starts counting when a locked transfer obtains access to the AXI bus.
When the counter reaches maximum value, a DDRB_LCKOUT
interrupt is generated and stays asserted until cleared by the
processor.
15
DDRB_HPD_WR_ERR
0
Asserted when the MSS DDR bridge gets an error response from the
DDR slave for an HPDMA write request. Address of write transaction
for which error response is received is provided by
DDRB_HPD_ERR_ADD.
14
DDRB_SW_WR_ERR
0
Asserted when the MSS DDR bridge gets an error response from the
DDR slave for an AHB bus master write request. Address of write
transaction for which error response is received is provided by
DDRB_SW_ERR_ADD.
13
DDRB_DS_WR_ERR
0
Asserted when the MSS DDR bridge gets an error response from the
DDR slave for a DS master write request. Address of write transaction
for which error response is received is provided by
DDRB_DS_ERR_ADD.
[12:7]
DDRB_RDWR_ERR_REG 0
Provides the read/write address match error status generated during
the following accesses:
Bit 0 = 1: AHB bus and HPDMA are trying to access same address
Bit 1 = 1: AHB bus and DS are trying to access same address
Bit 2 = 1: HPDMA and DS are trying to access same address
Bit 3 = 1: IDC and HPDMA are trying to access same address
Bit 4 = 1: IDC and AHB Bus are trying to access same address
Bit 5 = 1: IDC and DS are trying to access same address
[6:0]
SW_ERRORSTATUS
0
Indicates whether any accesses by the corresponding master on the
AHB bus resulted in either HRESP assertion by the slave to the AHB
bus, HRESP assertion by the AHB bus to that master (in the case of
blocked fabric master), or was decoded by the AHB bus as being to
“unimplemented” address space. The bit definitions are as follows:
Bit 0: Corresponds to an HRESP assertion being issued to the
HPDMA interface
Bit 1: Corresponds to an HRESP assertion being issued to FIC_0
interface
Bit 2: Corresponds to an HRESP assertion being issued to FIC_1
System interface S interface
Bit 3: Corresponds to an HRESP assertion being issued to the
Ethernet MAC
Bit 4: Corresponds to an HRESP assertion being issued to the
peripheral DMA engine
Bit 5: Corresponds to an HRESP assertion being issued to the USB
Bit 6: Corresponds to an HRESP assertion being issued to the
System Controller
These signals are not used as interrupts to the Cortex-M3 processor.
Instead, they are ORed together in SYSREG to create a signal called
SW_ERRORINTERRUPT, which is used as an interrupt to the
Cortex-M3 processor.
Table 757 •
MSS_EXTERNAL_SR
(continued)
Bit
Number Name
Reset
Value
Description