MMUART Peripherals
UG0331 User Guide Revision 15.0
484
13.2.4.6 Receiver Timeout
In the Receiver timeout block (Rx timeout), a counter looks for the post filtered serial input to remain High
until the counter expires. Once the timeout occurs, an RTOII interrupt is generated that is cleared when
the
register is rewritten.
Rx Timeout Value = 4 x RTO x Bit Time (Tbit)
13.2.4.7 LSB/MSB Orientation
MMUART_x allows either LSB or MSB to be received or transmitted first. LSB/MSB orientation is
mapped based on the Tx or Rx MSB bits of the
. Remapping of the serial I/O occurs at the APB
interface.
13.2.4.8 9-bit Transmit/Receive Mode
MMUART_x supports 9-bit address flag capability. The 9
th
bit mode is required for multi-drop addressing
topologies. Addressing mode is essentially 8-bit mode with 1 parity error bit or the 9
th
bit with parity set at
stick 0, which means that the parity is permanently set to 0 while receiving or transmitting data, an error
condition of 1 is used as an address flag, as shown in the following figure.
Figure 194 •
9-Bit Format
There are two ways to handle 9-bit multi-drop addressing:
•
Software Driven Parity Error Checking
: This is accomplished by configuring the MMUART in
8-bit mode, with stick 0 parity (SP bit in
) enabled. A parity error (PE) in the line status register
(
) is set whenever an address flag (AF) arrives by marking the address. Software can then
check this address byte to see if it matches its own address, and then proceed accordingly.
•
Automatic Hardware Address Flag Comparison
: When the automatic address flag comparison
option is enabled with the EAFM bit in the Multi-mode register 2 (
), the MMUART initially
disables the Rx FIFO and continuously checks for the address flag. If an address flag is received
and the associated 8-bit data matches the address in the
register, the Rx FIFO is enabled. In
this mode, the software does not check the address, and only receives Rx data once the address is
matched. Disabling the Rx FIFO occurs either by address flag being re-sent with a non-matching
address value (automatic), or the EAFC bit in
is set. An example for using EAFC takes place
when the address flag is received with the correct address. If the frame length is known to be 4
bytes, then the software could set the EAFC bit to disable the Rx FIFO after the 4th received byte,
and begin searching for another address flag with matching address.
13.2.4.9 Loopback Modes
There are two loopback modes: Local loopback mode and Remote loopback mode. In the Local
loopback mode, MMUART_X_TXD is set to 1. The MMUART_X_RXD, MMUART_X_DSR,
MMUART_X_CTS, MMUART_X_RI, and MMUART_X_DCD inputs are disconnected. The output of the
transmitter shift register is looped back into the receiver shift register. The modem control outputs
(MMUART_X_DTR, MMUART_X_RTS, MMUART_X_OUT1, and MMUART_X_OUT2) are connected
internally to the modem control inputs, and the modem control output pins are set as 1. The transmitted
data is immediately received, allowing the Cortex-M3 processor to check the operation of the
MMUART_X.
In Remote loopback mode, when a bit is received, it is sent directly out of the transmit line, bypassing the
transmitter block, and disabling the receiver. Local loopback has a higher priority over Remote loopback.
In Automatic echo mode, a bit is received and is sent directly out the transmit line, bypassing the
transmitter block, while the receiver is still enabled. Loopback modes can be enabled or disabled by
making changes to the modem control register (
).
Stop
Bit(s)
Address Byte Flag equal to
‘1’ during Address Fields
Address Byte
Start
Bit
A0
A5
A6
AF
A7
A4
A3
A2
A1