System Register Block
UG0331 User Guide Revision 15.0
712
22.3.50 DCode Miss Control Status Register
22.3.51 DCode Hit Control Status Register
22.3.52 ICode Transaction count Control Status Register
22.3.53 DCode Transaction Count Control Status Register
Table 707 •
CC_DC_MISS_CNTR_SR
Bit
Number Name
Reset
Value
Description
[31:0]
CC_DC_MISS_CNT
0
Counts the total number of cache misses that occurs on the
cacheable region through the DCode bus. Rolls back after
maximum value. This counter is put to the reset value by setting
CC_DC_MISS_CNTCLR.
Table 708 •
CC_DC_HIT_CNTR_CR
Bit
Number Name
Reset
Value
Description
[31:0]
CC_DC_HIT_CNT
0
Counts the total number of cache hits that occurs on the
cacheable region through the DCode bus. Rolls back after
maximum value. This counter is put to reset value by setting
CC_DC_HIT_CNTCLR.
Table 709 •
CC_IC_TRANS_CNTR_SR
Bit
Number Name
Reset
Value
Description
[31:0]
CC_IC_TRANS_CNT
0
Keeps count of the total number of transaction counts
processed by the cache engine (cacheable and non-cacheable
reads on ICode bus). This counter is put to the reset value by
setting CC_IC_TRAN_CNTCLR.
Table 710 •
CC_DC_TRANS_CNTR_SR
Bit
Number Name
Reset
Value
Description
[31:0]
CC_DC_TRANS_CNT
0
Keeps count of the total number of transaction counts
processed by the cache engine (cacheable and non-cacheable
reads on DCode bus). This counter is put to the reset value by
setting CC_DC_TRANS_CNTCLR bit.