Ethernet MAC
UG0331 User Guide Revision 15.0
396
0xBC
R/W
0x0
This is incremented for each received frame from 64 to 1518,
which contains an invalid FCS and is not an integral number of
bytes.
0XC0
R/W
0x0
This is incremented for each frame received in which the 802.3
length field does not match the number of data bytes actually
received (46 – 1500 bytes).
0XC4
R/W
0x0
This is incremented each time a valid carrier is present and at least
one invalid data symbol is detected.
0XC8
R/W
0x0
This is incremented each time a false carrier is detected.
0xCC
R/W
0x0
This is incremented each time a frame is received, which is less
than 64 bytes in length and contains a valid frame check sequence
(FCS).
0xD0
R/W
0x0
This is incremented each time a frame is received which
exceeds1518 (non VLAN) or 1522 (VLAN) bytes and contains a
valid FCS.
0xD4
R/W
0x0
This is incremented for each frame received which is less than 64
bytes in length and contains an invalid FCS.
0xD8
R/W
0x0
This is incremented for frames received which exceed 1518 (non
VLAN) or 1522 (VLAN) bytes and contains an invalid FCS.
0xDC
R/W
0x0
This is incremented for frames received which are streamed to
system but are later dropped due to lack of system resources.
Table 337 •
EMAC PE-MSTAT Transmit Counters Register Map
Register
Name
Address
Offset
Register
Type
Reset Value Description
0XE0
R/W
0x0
This is incremented for each transmitted byte including
fragments of frames which are involved in collisions.
0XE4
R/W
0x0
This is incremented for each transmitted packet.
0XE8
R/W
0x0
This is incremented for each transmitted multicast valid frame.
0xEC
R/W
0x0
This is incremented for each transmitted broadcast frame.
0XF0
R/W
0x0
This is incremented each time a valid PAUSE MAC control
frame is transmitted.
0XF4
R/W
0x0
This incremented for each frame, which is deferred on its first
transmission attempt.
0XF8
R/W
0x0
This is incremented for aborted frames, which are deferred for
an excessive period of time (3036 byte times).
0xFC
R/W
0x0
This is incremented for each transmitted frame that experiences
exactly one collision during the transmission.
0x100
R/W
0x0
This is incremented for each transmitted frame that experiences
2 to 15 collisions (including any late collisions) during the
transmission.
0x104
R/W
0x0
This is incremented for each transmitted frame which
experiences a late collision during a transmission attempt.
Table 336 •
EMAC PE-MSTAT Receive Counters Register Map
(continued)
Register
Name
Address
Offset
Register
Type
Reset
Value
Description