System Timer
UG0331 User Guide Revision 15.0
615
Figure 262 •
Timer Block Diagram
The Timer has an APB interface through which the Cortex-M3 processor can access various control and
status registers to control and monitor the operation of the Timer. The Timer consists of two 32-bit
decrementing counters. Counters generate the interrupts TIMER1INTand TIMER2INT on reaching zero.
Refer to the
page 622 for more information on Timer registers.
19.2.2
Port List
The following table lists the Timer ports.
19.2.2.1 Clocks
Timer is clocked by PCLK0 on the APB0 bus. PCLK is derived from the fabric alignment clock controller
(FACC) output. Refer to the
UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide
for
more information.
19.2.2.2 Resets
Timer resets to zero on power-up and is held in reset until enabled. Libero SoC software can reset the
Timer by writing to bit 6 of
in the SYSREG block. Soft reset bit definitions are
provided in the following table.
Table 613 •
Timer Interface Signals
Name
Type
Width
Description
TIMER1INT
Output
1
Active high interrupt from counter 1.
If enabled, this interrupt is asserted when counter 1 reaches zero.
In 64-bit mode this interrupt line is asserted when the
64-bit counter reaches zero.
TIMER2INT
Output
1
Active high interrupt from counter 2.
If enabled, this interrupt is asserted when counter 2 reaches zero.
Table 614 •
Soft Reset Bit Definitions for System Peripheral
Bit Number
Name
R/W
Reset Value
Description
6
TIMER_SOFTRESET
R/W
0x1
0: Releases the Timer from reset.
1: Keeps the Timer in reset.
PCLK
PRESETn
PSEL
PWRITE
PENABLE
PWDATA[31:0]
PRDATA[31:0]
TIMER1INT
TIMER2INT
Timer
APB Interface
Counter 1
Counter 2
Registers
PADDR[7:0]