Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
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3.5.2.8
Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. Some CMSIS provides intrinsic
functions for generation of these instructions. The following table lists the functions that CMSIS provides.
The actual exclusive access instruction generated depends on the data type of the pointer passed to the
intrinsic function.
3.5.3
Exception Model
This section describes the exception model.
3.5.3.1
Exception States
Each exception is in one of the following states:
Inactive:
The exception is not active and not pending.
Pending:
The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
Active:
An exception that is being serviced by the processor but has not completed. An exception
handler can interrupt the execution of another exception handler. In this case both exceptions are in the
active state.
Active and pending:
The exception is being serviced by the processor and there is a pending exception
from the same source.
3.5.3.2
Exception Types
The exception types are:
Reset:
Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in
an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry
in the vector table. Execution restarts as privileged execution in Thread mode.
NMI:
A Non-Maskable Interrupt (NMI) can be signaled by a peripheral or triggered by software. This is
the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2.
NMIs cannot be:
•
masked or prevented from activation by any other exception.
•
preempted by any exception other than Reset.
HardFault:
A HardFault is an exception that occurs because of an error during exception processing, or
because an exception cannot be managed by any other exception mechanism. HardFaults have a fixed
priority of -1, meaning they have higher priority than any exception with configurable priority.
Table 21 •
CMSIS Functions for Exclusive Access Instructions
Instruction
Intrinsic Function
LDREX, LDREXH, or LDREXB
unsigned char__LDREXB(volatile char *ptr)
unsigned short __LDREXH(volatile short *ptr)
unsigned int __LDREXB(volatile int *ptr)
STREX, STREXH, or STREXB
int __STREXB(unsigned char val, volatile char *ptr)
int __STREXB(unsigned short val, volatile short *ptr)
int __STREXB(unsigned int val, volatile int *ptr)
CLREX
void __CLREX(void)