Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
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3.5.1.3.10 CONTROL Register
The CONTROL register controls the stack used and the privilege level for software execution when the
processor is in Thread mode. Refer to the register summary in
page 21 for its attributes. The
following figure shows the bit assignments for MSR or MRS access.
Figure 10 •
Control Register
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer
bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms
automatically update the CONTROL register based on the EXC_RETURN value, see
In an OS environment, ARM recommends that threads running in Thread mode use the process stack
and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP,
either:
•
use the MSR instruction to set the Active stack pointer bit to 1, see
•
perform an exception return to Thread mode with the appropriate EXC_RETURN value, see
Note:
When changing the stack pointer, software must use an ISB instruction immediately after the MSR
instruction. This ensures that instructions after the ISB instruction execute using the new stack pointer.
Refer to
Table 16 •
Control Register Bit Assignments
Bits
Name
Function
[31:2]
Reserved
[1]
Active stack pointer
Defines the currently active stack pointer:
0: MSP is the current stack pointer
1: PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
[0]
Thread mode privilege
level
Defines the Thread mode privilege level:
0: Privileged
1: Unprivileged.
Reserved
31
2 1 0
Active Stake Pointer
Thread Mode Privilege Level