Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
74
3.6.5.7
MOVT
Move Top.
3.6.5.7.1
Syntax
MOVT{cond} Rd, #imm16
where:
cond
is an optional condition code, see
Rd
is the destination register.
imm16
is a 16-bit immediate constant.
3.6.5.7.2
Operation
MOVT writes a 16-bit immediate value,
imm16
, to the top halfword,
Rd
[31:16], of its destination register.
The write does not affect
Rd
[15:0].
The MOV, MOVT instruction pair enables you to generate any 32-bit constant.
3.6.5.7.3
Restrictions
Rd
must not be SP and must not be PC.
3.6.5.7.4
Condition Flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
3.6.5.8
REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
3.6.5.8.1
Syntax
op{cond} Rd, Rn
where:
•
op
is any of:
•
REV
:
Reverse byte order in a word.
•
REV16
:
Reverse byte order in each halfword independently.
•
REVSH
:
Reverse byte order in the bottom halfword, and sign extend to 32 bits.
•
RBIT
:
Reverse the bit order in a 32-bit word.
•
cond
is an optional condition code, see
•
Rd
is the destination register.
•
Rn
is the register holding the operand.
3.6.5.8.2
Operation
Use these instructions to change endianness of data:
•
REV
:
converts 32-bit big-endian data into little-endian data or 32-bit little-endian data into big-endian
data.
•
REV16
:
converts 16-bit big-endian data into little-endian data or 16-bit little-endian data into
big-endian data.
•
REVSH
:
converts either:
•
16-bit signed big-endian data into 32-bit signed little-endian data
•
16-bit signed little-endian data into 32-bit signed big-endian data.
3.6.5.8.3
Restrictions
Do not use SP and do not use PC
.