Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
71
•
n
is the shift length. The range of shift length depends on the instruction:
•
ASR
shift length from 1 to 32
•
LSL
shift length from 0 to 31
•
LSR
shift length from 1 to 32
•
ROR
shift length from 1 to 31
Note:
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
3.6.5.3.2
Operation
ASR, LSL, LSR, and ROR move the bits in the register
Rm
to the left or right by the number of places
specified by constant
n
or register
Rs
.
RRX moves the bits in register
Rm
to the right by 1.
In all these instructions, the result is written to
Rd
, but the value in register
Rm
remains unchanged. For
details on what result is generated by the different instructions, see
3.6.5.3.3
Restrictions
Do not use SP and do not use PC.
3.6.5.3.4
Condition Flags
If S is specified:
•
these instructions update the N and Z flags according to the result
•
the C flag is updated to the last bit shifted out, except when the shift length is 0, see
Examples
ASR R7, R8, #9 ; Arithmetic shift right by 9 bits
LSLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend.
3.6.5.4
CLZ
Count Leading Zeros.
3.6.5.4.1
Syntax
CLZ{cond} Rd, Rm
where:
cond
is an optional condition code, see
Rd
is the destination register.
Rm
is the operand register.
3.6.5.4.2
Operation
The CLZ instruction counts the number of leading zeros in the value in
Rm
and returns the result in
Rd
.
The result value is 32 if no bits are set and zero if bit[31] is set.
3.6.5.4.3
Restrictions
Do not use SP, and do not use PC.