System Register Block
UG0331 User Guide Revision 15.0
694
Reset values in the preceding table are the default values of the bits when peripherals are not configured
using the software. If the peripheral is enabled using the software then the default reset value for that bit
is 0x0.
Note:
Do not change these register fields dynamically for 005 and 010 devices, see
13
CAN_SOFTRESET
0x1
0: Releases CAN from reset
1: Keeps CAN in reset
12
I2C1_SOFTRESET
0x1
0: Releases I2C_1 from reset
1: Keeps I2C_1 in reset
11
I2C0_SOFTRESET
0x1
0: Releases I2C_0 from reset
1: Keeps I2C_0 in reset
10
SPI1_SOFTRESET
0x1
0: Releases SPI1 from reset
1: Keeps SPI1 in reset
9
SPI0_SOFTRESET
0x1
0: Releases SPI0 from reset
1: Keeps SPI0in reset
8
MMUART1_SOFTRESET
0x1
0: Releases MMUART_1 from reset
1: Keeps MMUART_1 in reset
7
MMUART0_SOFTRESET
0x1
0: Releases MMUART_0 from reset
1: Keeps MMUART_0 in reset
6
TIMER_SOFTRESET
0x1
0: Releases the system timer from reset
1: Keeps the system timer in reset
5
PDMA_SOFTRESET
0x1
0: Releases the PDMA from reset
1: Keeps the PDMA in reset
4
MAC_SOFTRESET
0x1
0: Releases the Ethernet MAC from reset
1: Keeps the Ethernet MAC in reset
3
ESRAM1_SOFTRESET
0
0: Releases the eSRAM_1 memory controller from
reset
1: Keeps the eSRAM_1 memory controller in reset
2
ESRAM0_SOFTRESET
0
0: Releases the eSRAM_0 memory controller from
reset
1: Keeps the eSRAM_0 memory controller in reset
1
ENVM1_SOFTRESET
0
0: Releases the eNVM_1memory controller from reset
1: Keeps the eNVM_1 memory controller in reset
0
ENVM0_SOFTRESET
0
0: Releases the eNVM_0 memory controller from reset
1: Keeps the eNVM_0 memory controller in reset
Table 674 •
SOFT_RESET_CR
(continued)
Bit
Number Name
Reset
Value
Description