Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
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3.5.1.4
Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except for
reset. Refer to
The NVIC registers control interrupt handling. See
Nested Vectored Interrupt Controller,
more information.
The following sections provide more information about the CMSIS
•
Power Management Programming Hints,
•
•
Accessing the Cortex-M3 Processor NVIC Registers Using CMSIS,
•
3.5.1.5
Data types
The processor:
•
supports the following data types:
•
32-bit words
•
16-bit halfwords
•
8-bit bytes.
•
manages all data memory accesses as little-endian or big-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always performed as little-endian. The Cortex-M3 processor
configured for SmartFusion2 SoC FPGA MSS uses only little-endian. Refer to
3.5.1.6
The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 processor system, the Cortex Microcontroller Software Interface Standard (CMSIS)
defines:
•
a common way to:
•
access peripheral registers
•
define exception vectors
•
the names of:
•
the registers of the core peripherals
•
the core exception vectors
•
a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3
processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack
and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the combination of
CMSIS-compliant software components from various middleware vendors. Software vendors can expand
the CMSIS to include their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the
CMSIS functions that address the processor core and the core peripherals.
Note:
This document uses the register short names defined by the CMSIS. In a few cases these differ from the
architectural short names that might be used in other documents.