System Register Block
UG0331 User Guide Revision 15.0
706
25
PERSIST_CC
0
Feeds into the MSS Reset Controller. Based on the value of
PERSIST_CC, the Reset Controller asserts a reset
(CC_RESET_N) to the FACC (which inverts it and passes it on
to the PLL as MSSDDR_PLL_RESET), either on every MSS
system reset or just on power-up reset.
This field is to be configured using flash bits. Do not write to this
field. The only allowable value for this bit is 1. The reset signal
for this register is PORESET_N.
[24:22]
BASE_DIVISOR
0
Indicates the ratio between CLK_A and the re-generated
version of CLK_BASE, called CLK_BASE_REGEN. Do not
write to this field.
The allowed values are listed in
[21:19]
DDR_FIC_DIVISOR
0
Indicates the ratio between CLK_A and DDR_SMC_FIC_CLK.
The user can write to this field dynamically during run time,
even when the source clock is active. The allowed values are
listed in
[18:16]
FIC_1_DIVISOR
0
Indicates the ratio between CLK_A and the clock being used in
the fabric, to clock the soft IP block which is interfacing to FIC_1
of the MSS. The user can write to this field dynamically during
run time, even when the source clock is active. The allowed
ratios for CLK_A:fabric clock (FIC_1) is listed in
[15:13]
FIC_0_DIVISOR
0
Indicates the ratio between CLK_A and the clock being used in
the fabric, to clock the soft IP block which is interfacing to FIC_0
of the MSS. The user can write to this field dynamically during
run time, even when the source clock is active. The allowed
ratios for CLK_A:fabric clock (FIC_0) are listed in
12
FACC_GLMUX_SEL
0
Contains the select line for the four no-glitch multiplexers within
the FACC, which are related to the aligned clocks. All four of
these multiplexers are switched by one signal. Allowed values:
1: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK
all driven from CLK_STANDBY
0: M3_CLK, APB_0_CLK, APB_1_CLK, DDR_SMC_FIC_CLK
all driven from stage B dividers
Configure this field using flash bits. Do not write to this field.
[11:9]
M3_CLK_DIVISOR
0
Indicates the ratio between CLK_A and M3_CLK. The user can
write to this field dynamically during run time, even when the
source clock is active.
8
DDR_CLK_EN
0
Determines whether or not the clock to the MDDR block is to be
gated off. Allowed values:
0: MDDR_CLK is gated off
1: MDDR_CLK is allowed to propagate through to MDDR block
Do not write to this field dynamically while the source clock is
active.
[7:5]
APB1_DIVISOR
0
Indicates the ratio between CLK_A and APB_1_CLK. The user
can write to this field dynamically during run time, even when
the source clock is active. The allowed values are described in
Table 694 •
MSSDDR_FACC1_CR
(continued)
Bit Number Name
Reset
Value
Description