Peripheral DMA
UG0331 User Guide Revision 15.0
280
The following table gives the PERIPHERAL_SEL bits description.
7
CLR_COMP_A
0
When asserted, clears the CH_COMP_A bit in the channel status
register and the buffer status register for this buffer in this channel.
This causes PDMAINTERRUPT to negate if not being held asserted
by another channel. This bit always reads back as zero.
6
INTEN
0
When asserted, a DMA completion on this channel causes
PDMAINTERRUPT to assert.
5
RESET
0
When asserted, resets this channel. Always reads back as zero.
4
PAUSE
0
When asserted, pauses the transfers for this channel.
[3:2]
TRANSFER_SIZE
00
This field determines the data width of each DMA transfer cycle for
this DMA channel. The allowed values are:
00: Byte (8 bits)
01: Halfword (16 bits)
10: Word (32 bits)
11: Reserved
1
DIR
0
If PERIPHERAL_DMA = 1, then this bit is valid. If so, then the
values of this bit have the following meanings:
0: Peripheral to memory
1: Memory to peripheral
0
PERIPHERAL_DM
A
0
0: Channel is configured for memory to memory DMA.
1: Channel is configured for peripheral DMA. Based on the value of
DIR, the peripheral ready signal associated with this DMA channel
is interpreted as initiating transfers either from memory to the
peripheral or vice-versa.
Table 181 •
PERIPHERAL_SEL
Bit 26
Bit 25 Bit 24
Bit 23
Function
0
0
0
0
From UART_0 receive to any MSS memory-mapped location
0
0
0
1
From any MSS memory-mapped location to UART_0 transmit
0
0
1
0
From UART_1 receive to any MSS memory-mapped location
0
0
1
1
From any MSS memory-mapped location to UART_1 transmit
0
1
0
0
From SPI_0 receive to any MSS memory-mapped location
0
1
0
1
From any MSS memory-mapped location to SPI_0 transmit
0
1
1
0
From SPI_1 receive to any MSS memory-mapped location
0
1
1
1
From any MSS memory-mapped location to SPI_1 transmit
1
0
0
0
To/from FPGA fabric peripheral on FIC_0 interface (DMAREADY_0[1])
1
0
0
1
To/from FPGA fabric peripheral on FIC_0 interface (DMAREADY_0[0])
1
0
1
0
From any MSS memory-mapped location to CAN
1
0
1
1
From CAN to any MSS memory-mapped location
1
1
0
0
To/from FPGA fabric peripheral on FIC_1 interface (DMAREADY_1[1]).
1
1
0
1
To/from FPGA fabric peripheral on FIC_1 interface (DMAREADY_1[0]).
1
1
1
0
From COMM_BLK receive to any MSS memory-mapped location
1
1
1
1
From any MSS memory-mapped location to COMM_BLK transmit
Table 180 •
CHANNEL_x_CONTROL
(continued)
Bit Number Name
Reset Value Description