Reset Controller
UG0331 User Guide Revision 15.0
655
The generation of SYSRESET_N is shown in the following figure.
Figure 286 •
SYSRESET_N Generation
The inputs SYS_RESET_REQ_N, LOCKUP_N, WD_TIMEOUT_N, SC_MSS_RESET_N, and
MSS_RESET_N_F2M are first synchronized on M3_CLK and then combined. The
MSS_RESET_N_F2M signal can be used to reset the MSS, independently of any resets coming from the
MSS itself. For example it may be asserted as a result of an external reset event from an off-chip Reset
Controller, using an I/O pad to bring the reset input into the fabric.
The following figure shows the various reset signals to the MSS blocks which are generated from Reset
Controller on assertion of SYSRESET_N. It also shows the reset inputs to the Reset Controller, which
cause the generation of SYSRESET_N.
Figure 287 •
Functional Block Diagram of Reset Controller During SYSRESET_N
SYSRESET_N resets all blocks in the MSS. When SYSRESET_N asserts low, the entire Cortex-M3
processor is reset, except for the debug logic that exists in the following blocks:
•
Nested vectored interrupt controller (NVIC)
•
Flash patch and breakpoint (FPB)
•
Data watchpoint and trace (DWT)
FFs
MSS_RESET_N_F2M
SC_MSS_RESET_N
WD_TIMEOUT_N
SYS_RESET_REQ_N
LOCKUP_N
M3_CLK
1
SYSRESET_N
R
Reset Controller
Watchdog
Timer
WD_TIMEOUT
Peripherals
SC_MSS_RESET_N
FPGA
Fabric
MSS_RESET_N_F2M
MSS_RESET_N_M2F
WDOG_RESET_N
SYSREG
SYSRESET_N
Cortex-M3
Processor
SYS_RESET_REQ
LOCKUP
M3_SYS_RESET_N
M3_TRST_N
FIC_2_APB_M_PRESET_N
System
Controller
MDDR
MDDR_AXI_RESET_N
MDDR_APB_RESET_N
Block Resets