Reset Controller
UG0331 User Guide Revision 15.0
663
21.3.1.3 SERDES L2/P2, PRST#
L2 and P2 are low power states for the Link and PHY interface in a PCI Express (PCIe) system. A power
management component in a PCIe system will control exit from the L2/P2 state. Part of the sequence
when emerging from the low power state involves assertion and release of the PCI Express Reset
(PERST# or SDIFx_PERST_N in our implementation). CoreResetP monitors SDIFx_PERST signals and
L2/P2 state and generates CORE reset and PHY reset to fulfill the low power mode reset requirement.
The following figure shows the CoreResetP connectivity with SERDES_IF block. If the System Builder is
used to generate the Libero project, all required cores are Instantiated, and connections are made
automatically.
Figure 298 •
CoreResetP Connectivity with SERDES_IF Block
21.3.2
Implementation
If the System Builder tool is used within the Libero SoC software to construct a design targeted at a
SmartFusion2 device, CoreResetP will automatically be instantiated and connected within the design if
required. You can manually instantiate and configure CoreResetP within a SmartDesign design if
required. Refer to the CoreResetP Handbook for connecting and configuring CoreResetP in
SmartDesign.
Note:
CoreConfigP soft IP facilitates configuration of peripheral blocks (MDDR, FDDR, and SERDESIF blocks)
in a SmartFusion2 devices. CoreConfigP is available in the Libero SoC IP Catalog. Refer to the
CoreConfigP Handbook for port lists and their descriptions, design flows, memory maps, and Control and
Status register details.
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