Cortex-M3 Processor Overview and Debug Features
UG0331 User Guide Revision 15.0
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2.4
Cortex-M3 Processor SysTick Timer
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero,
reloads, that is, wraps to the value in the SYST_RVR register on the next clock edge, and then counts
down on subsequent clocks. The SysTick timer is used to generate a periodic interrupt to the Cortex-M3
processor. The SysTick can be polled by the software or it can be configured to generate an interrupt.
The SysTick interrupt has its own entry in the vector table and therefore its own handler.
2.5
Cortex-M3 Processor Debug Subsystem
2.5.1
Cortex-M3 Processor Debug Port
The debug port uses a serial wire (SW) JTAG debug port (SWJ-DP). This enables either the JTAG or the
SW protocol to be used for debugging. The SWJ-DP defaults to JTAG mode at power-up and can be
switched to SW by applying a specific sequence to the debug pins.
The trace port interface unit (TPIU) is configured to support ITM debug trace and ETM debug trace.
Serial wire mode is used for the TPIU output data and this is overlaid on the JTAG TDO port. One
implication of this is that instrumentation trace cannot be used along with JTAG-based debugging. SW
debugging and ITM can be used together.
The Cortex-M3 processor provides the following debug Interfaces:
•
SWJ-DP: JTAG is the industry-standard interface used to download and debug programs on a target
processor, as well as for other functions. It offers access to all of the Cortex-M3 processor
CoreSight
®
debug capabilities.
•
SW-DP: The serial wire debug (SWD) mode is an alternative to the standard JTAG interface. SWD
uses two pins to provide the same debug functionality as JTAG with no performance penalty, and
introduces data trace capabilities with the serial wire viewer (SWV). The SWD interface pins are
overlaid with the JTAG signals, allowing standard target connectors to be used.
•
TCLK: SWCLK (serial wire clock)
•
TMS: SWDIO (serial wire debug data input/output)
INTISR[66] GPIO_INT[16]
GPIO
Interrupt from GPIO
INTISR[67] GPIO_INT[17]
GPIO
Interrupt from GPIO
INTISR[68] GPIO_INT[18]
GPIO
Interrupt from GPIO
INTISR[69] GPIO_INT[19]
GPIO
Interrupt from GPIO
INTISR[70] GPIO_INT[20]
GPIO
Interrupt from GPIO
INTISR[71] GPIO_INT[21]
GPIO
Interrupt from GPIO
INTISR[72] GPIO_INT[22]
GPIO
Interrupt from GPIO
INTISR[73] GPIO_INT[23]
GPIO
Interrupt from GPIO
INTISR[74] GPIO_INT[24]
GPIO
Interrupt from GPIO
INTISR[75] GPIO_INT[25]
GPIO
Interrupt from GPIO
INTISR[76] GPIO_INT[26]
GPIO
Interrupt from GPIO
INTISR[77] GPIO_INT[27]
GPIO
Interrupt from GPIO
INTISR[78] GPIO_INT[28]
GPIO
Interrupt from GPIO
INTISR[79] GPIO_INT[29]
GPIO
Interrupt from GPIO
INTISR[80] GPIO_INT[30]
GPIO
Interrupt from GPIO
INTISR[81] GPIO_INT[31]
GPIO
Interrupt from GPIO
Table 2 •
Cortex-M3 Processor Interrupts
(continued)
Cortex-M3
Interrupt
Signal
Source
Description