Universal Serial Bus OTG Controller
UG0331 User Guide Revision 15.0
341
10.3.9.10 Encoded UTMI Event Signals
10.3.9.11 EP_INFO_REG Bit Definitions
10.3.9.12 RAM_INFO_REG Bit Definitions
10.3.9.13 LINK_INFO_REG Bit Definitions
[1:0]
LineState[1:0]
0
UTMI+ LineState signals
Table 262 •
Encoded UTMI Event Signals
Value
RxActive
RxError
Host Disconnect
00
0
0
0
01
1
0
0
10
1
1
0
11
X
X
1
Table 263 •
EP_INFO_REG (0x40043078)
Bit
Number Name
Reset
Value
Function
[7:4]
RxEndPoints
0
The number of receive endpoints implemented in the design.
[3:0]
TxEndPoints
0
The number of transmit endpoints implemented in the design.
Table 264 •
RAM_INFO_REG (0x40043079)
Bit
Number Name
Reset
Value
Function
[7:4]
DMAChans
0
The number of DMA channels implemented in the design
[3:0]
RamBits
0
The width of the RAM address bus
Table 265 •
LINK_INFO_REG (0x4004307A)
Bit
Number Name
Reset
Value
Function
[7:4]
WTCON
0x5
Sets the wait to be applied to allow for the connect/disconnect filter in
units of 533.3 ns. The default setting corresponds to 2.667 μs.
[3:0]
WTID
0xC
Sets the delay to be applied from IDPULLUP being asserted to IDDIG
being considered valid in units of 4.369 ms. The default setting
corresponds to 52.43 ms.
Table 261 •
ULPI_RAW_DATA_REG (0x40043077) (Synchronous)
(continued)
Bit
Number Name
Reset
Value
Function