Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
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code overhead from the ISRs. A Tail-chain optimization also significantly reduces the overhead when
switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep
function that enables the entire device to be rapidly powered down while still retaining program state.
3.1
System Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA
®
technology to provide high speed,
low latency memory accesses. It supports unaligned data accesses and implements atomic bit
manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data
handling.
The Cortex-M3 processor has an optional memory protection unit (MPU) that provides fine grain memory
control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and
stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications
such as automotive systems.
3.2
Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution. This provides high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small package devices. The MCU vendor
determines the debug feature configuration and therefore this can differ across different devices and
families.
For system trace the processor integrates an Instrumentation Trace Macrocell™ (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these
generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace,
and profiling information through a single pin.
The optional Embedded Trace Macrocell (ETM) delivers unrivaled instruction trace capture in an area far
smaller than traditional trace units, enabling many low cost MCUs to implement full instruction trace for
the first time.
The optional Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint
comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to
eight words in the program code in the CODE memory region. This enables applications stored on a non-
erasable, ROM-based microcontroller to be patched if a small programmable memory, for example flash,
is available in the device. During initialization, the application in ROM detects, from the programmable
memory, whether a patch is required. If a patch is required, the application programs the FPB to remap a
number of addresses. When those addresses are accessed, the accesses are redirected to a remap
table specified in the FPB configuration, which means the program in the non-modifiable ROM can be
patched.
3.3
Cortex-M3 Processor Features and Benefits Summary
•
Tight integration of system peripherals reduces area and development costs.
•
Thumb instruction set combines high code density with 32-bit performance.
•
Code-patch ability for ROM system updates.
•
Power control optimization of system components.
•
Integrated Sleep modes for low power consumption.
•
Fast code execution permits slower processor clock or increases sleep mode time.
•
Hardware division and fast multiplier.
•
Deterministic, high-performance interrupt handling for time-critical applications.
•
Optional memory protection unit (MPU) for safety-critical applications.
•
Extensive debug and trace capabilities—Serial Wire Debug and Serial Wire Trace reduce the
number of pins required for debugging, tracing and code profiling.