Inter-Integrated Circuit Peripherals
UG0331 User Guide Revision 15.0
561
15.4.7
Glitch Register
The Glitch register (GLITCHREG) gives the size of the glitch (in terms of APB interface clock cycles) to
filter the glitches on data and clock lines.
15.4.8
Slave1 Address Register
The I
2
C has dual slave address (Slave0/Slave1) decoding capability. The Slave0 address register is a
read/write directly accessible register. The details of this register are provided in the following table.
Table 533 •
Glitch Register (GLITCHREG)
Bit
Number Name
R/W
Reset
Value
Description
7:0
GlitchReg_Num R/W
0x03
This read/write register is used to adjust the input glitch filter length.
Depending on the application, the glitch filter is used to suppress spikes
between 3 and 21 APB interface clock cycles. Number or length of shift
register filter is set to value from 3 to 21.
Table 534 •
Slave1 Address Register (SLAVE1 ADR)
Bit
Number
Name
R/W
Reset
Value
Description
7
ADR6
R/W
0
Own Slave1 address bit 6
6
ADR5
R/W
0
Own Slave1 address bit 5
5
ADR4
R/W
0
Own Slave1 address bit 4
4
ADR3
R/W
0
Own Slave1 address bit 3
3
ADR2
R/W
0
Own Slave1 address bit 2
2
ADR1
R/W
0
Own Slave1 address bit 1
1
ADR0
R/W
0
Own Slave1 address bit 0
0
ENADR
R/W
0
1: Enable the Slave1 address comparisons
0: Disable Slave1 address comparisons