Embedded SRAM (eSRAM) Controllers
UG0331 User Guide Revision 15.0
189
The following figure shows the eSRAM controller blocks and their connectivity in SmartFusion2 FPGAs.
Both eSRAMs and eSRAM controllers are identical in all design aspects.
Figure 96 •
eSRAM Controller Block Diagram
M3_CLK is used within the MSS to clock the AHB bus matrix. Refer to
IGLOO2 Clocking Resources User Guide
for more information on M3_CLK.
AHBL Interface:
Each eSRAM controller is an AHB-Lite (AHBL) slave that provides access to the
eSRAM block from the AHB bus matrix.
ECC Generator and Data MUX:
In SECDED-ON mode, the ECC Generator generates the check bits for
32-bit data. For a 32-bit write from the AHBL interface, the input data AHB write data bus (HWDATA) is
used to generate check bits. These check bits are appended to HWDATA and written to the memory. For
8-bit and 16-bit writes from the AHBL interface, a read-modify-write operation is used. This reads data
from the 32-bit word, corrects if necessary, and then writes the new data value and ECC check bits.
In SECDED-OFF mode, if the memory access is within 32 KB memory, HWDATA is sent directly to the
memory input. If the access is for additional 8 KB memory, then the address for a particular byte of
HWDATA will be selected based on the shift address.
Address MUX:
This utilizes the AHB address bus (HADDR) and HADDRU (an additional HADDR bit) for
selecting upper 8 K bank of the RAM. Based on the FSM internal signals, output ADDR is generated and
passed to the memory. The shifted address is also generated and used for multiplexing data.
FSM:
This generates output signal HREADYOUT and internal signals that are used for multiplexing an
address.
Pipeline:
A pipeline stage in the read path of eSRAM and the master that accesses this path is
configurable using the ESRAM_PIPELINE_ENABLE signal. When ESRAM_PIPELINE_ENABLE is High,
there is an extra one clock cycle delay for the read operation to maximize operational frequency. At
higher frequencies (> 100 MHz) of Cortex-M3 or other masters accessing eSRAM, the eSRAM
operations need an extra clock cycle for the correct data transactions.
AHBL
INTERFACE
ECC
GENERATOR
& DATA MUX
ADDRESS
MUX
FSM
PIPELINE
ECC
CHECKER &
HRDATA
GENERATOR
RAM
4096X40_0
RAM
4096X40_1
ERROR
STATUS
SIGNAL
EDAC_AD
EDAC_1E
EDAC_2E
HWDATA
ADDR
HADDRU
HSEL
HREADY
HTRANS
HREADYOUT
HRDATA
HRESP
WEB_0
CSB
DO
SELECT
DO_0
DO_1
DI_0
DI_1
WEB_1
DO
DO
HADDR
ESRAM_PIPELI
NE_ENABLE
AHBL Interface
AHB
BUS
Matrix
M3_CLK