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Microsemi SmartFusion2 MSS, User Manual

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Universal Serial Bus OTG Controller

UG0331 User Guide Revision 15.0

323

10.3.6.10 RX_MAX_P_REG Bit Definitions

0

Data Toggle 

0

When read, this bit indicates the current state of the endpoint 0 data toggle. If 
Data Toggle Write Enable (bit 1 of this register) is High, this bit may be written 
with the required setting of the data toggle. If Data Toggle Write Enable is Low, 
any value written to this bit is ignored.

Table 221 • 

RX_MAX_P_REG

Bit 
Number

Name

Reset 
Value

Function

[15:11]

m-1

N/A

If the core is configured for high-bandwidth ISO/interrupt endpoints or packet splitting 
on bulk endpoints, the register includes either 2 or 5 further bits that define a multiplier 

m, 

which is equal to one more than the value recorded.

For bulk endpoints with the packet splitting option enabled, the multiplier 

m 

can be up 

to 32 and defines the number of USB packets of the specified payload which are to be 
amalgamated into a single data packet within the FIFO. If the packet splitting option is 
not enabled, bits[15:13] are not implemented and bits[12:11] (if included) are ignored.
For ISO/interrupt endpoints operating in High speed mode and with the 
high-bandwidth option enabled, 

m 

may only be either 2 or 3 (corresponding to bit 11 

set or bit 12 set) and it specifies the maximum number of such transactions that can 
take place in a single microframe. If either bit[11] or bit[12] is non-zero, the USB 
controller automatically combines the separate USB packets received in any 
microframe into a single packet within the receive FIFO. The maximum payload for 
each transaction is 1,024 bytes, so this allows up to 3,072 bytes to be

 

received in 

each microframe. For ISO transfers in Full speed mode or if high-bandwidth is not 
enabled, bits[11] and [12] are ignored.
The value written to bits[10:0] (multiplied by 

m 

in the case of high-bandwidth ISO 

transfers) must match the value given in the 

wMaxPacketSize 

field of the standard 

endpoint descriptor for the associated endpoint (refer to the 

USB specification 

revision 2.0,
Chapter 9). A mismatch could cause unexpected results.
The total amount of data represented by the value written to this register (specified 
payload × 

m

) must not exceed the FIFO size for the receive endpoint, and should not 

exceed half the FIFO size if double-buffering is required.

[10:0]

RxMaxP

0

Maximum payload/transaction. Maximum payload in bytes received in a single 
transaction. The value set can be up to 1,024 bytes but is subject to the constraints 
placed by the USB specification on packet sizes for bulk, interrupt, and ISO transfers 
in full speed and high speed operations.
RxMaxP must be set to an even number of bytes for proper interrupt generation in 
DMA Mode 1.

Table 220 • 

TX_CSRH_REG (Host)

 (continued)

Bit 
Number

Name

Reset 
Value

Function

Summary of Contents for SmartFusion2 MSS

Page 1: ...UG0331 User Guide SmartFusion2 Microcontroller Subsystem ...

Page 2: ...ne suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such information is entirely with the Buyer Microsemi does not grant explicitly or implicitly to any party any patent rights licenses or any other IP rights whether with regard to such information itself or...

Page 3: ...or Trace System 13 2 6 Cortex M3 Processor Port Descriptions 15 2 7 How to Use the Cortex M3 Processor and the Debug Subsystem 16 2 7 1 Configuration Through Libero Software and Firmware 16 3 Cortex M3 Processor Reference Material 18 3 1 System Level Interface 19 3 2 Integrated Configurable Debug 19 3 3 Cortex M3 Processor Features and Benefits Summary 19 3 4 Cortex M3 Processor Core Peripherals 2...

Page 4: ...mbedded NVM eNVM Controllers 145 5 1 Features 145 5 2 Functional Description 146 5 2 1 Memory Organization 147 5 2 2 Data Retention Time 148 5 2 3 eNVM Access Time 148 5 2 4 Theory of Operation 148 5 2 5 eNVM Command Register 151 5 2 6 Error Response 159 5 2 7 Interrupt to Cortex M3 Processor 159 5 3 Security 159 5 3 1 User Protectable 4K Regions 160 5 3 2 eNVM Pages for Special Purpose Storage 16...

Page 5: ...2 PDMA Use Models 274 9 4 PDMA Register Map 275 9 4 1 PDMA Configuration Register Bit Definitions 278 9 5 SYSREG Control Registers 283 10 Universal Serial Bus OTG Controller 284 10 1 Features 284 10 2 Functional Description 285 10 2 1 Architecture Overview 285 10 2 2 USB OTG Controller Interface Signals 287 10 2 3 USB OTG Controller Operations 291 10 3 How to Use USB OTG Controller 300 10 3 1 Libe...

Page 6: ...ctional Description 437 12 2 1 CAN Controller Interface Signals 437 12 2 2 Transmit Procedures 438 12 2 3 Receive Procedures 439 12 2 4 Interrupt Generation 441 12 2 5 CAN Test Modes 442 12 3 CAN Controller Configuration 442 12 3 1 Peripheral Signals Assignment Table 443 12 3 2 EDAC CAN Configuration 444 12 4 How to Use the MSS CAN Controller 446 12 4 1 Hardware Design Flow 446 12 5 Use Cases 448 ...

Page 7: ... Scratch Register SR 500 13 4 14 Multi Mode Control Register 0 MM0 500 13 4 15 Multi Mode Control Register 1 MM1 501 13 4 16 Multi Mode Control Register 2 MM2 501 13 4 17 Glitch Filter Register GFR 502 13 4 18 Transmitter Time Guard Register TTG 503 13 4 19 Receiver Timeout Register RTO 503 13 4 20 Address Register ADR 503 14 Serial Peripheral Interface Controller 504 14 1 Features 504 14 2 Functi...

Page 8: ... Source Select Control Register 577 16 4 6 GPIO System Reset Control Register 578 16 4 7 I O MUX Associated With GPIOs 578 17 Communication Block 592 17 1 Features 592 17 2 Functional Description 593 17 2 1 Architecture Overview 593 17 2 2 Frame Command Marker 594 17 2 3 Clocks 595 17 2 4 Resets 595 17 2 5 Interrupts 595 17 2 6 COMM_BLK Initialization 595 17 2 7 CoreSysServices Soft IP 595 17 3 Ho...

Page 9: ...Interrupt Status Register 625 19 4 6 Timer 64 Value Upper Register 625 19 4 7 Timer 64 Value Lower Register 625 19 4 8 Timer 64 Load Value Upper Register 625 19 4 9 Timer 64 Load Value Lower Register 626 19 4 10 Timer 64 Background Load Value Upper Register 626 19 4 11 Timer 64 Background Load Value Lower Register 627 19 4 12 Timer 64 Control Register 627 19 4 13 Timer 64 Raw Interrupt Status Regi...

Page 10: ...22 3 6 eNVM Remap Base Address Control Register 686 22 3 7 eNVM FPGA Fabric Remap Base Address Register 687 22 3 8 Cache Configuration Register 687 22 3 9 Cache Region Control Register 688 22 3 10 Cache Lock Base Address Control Register 688 22 3 11 Cache Flush Index Control Register 688 22 3 12 MSS DDR Bridge Buffer Timer Control Register 689 22 3 13 MSS DDR Bridge Non Bufferable Address Control ...

Page 11: ...MSS DDR Bridge AHB Bus Error Address Status Register 713 22 3 57 MSS DDR Bridge Buffer Empty Status Register 714 22 3 58 MSS DDR Bridge Disable Buffer Status Register 714 22 3 59 eSRAM0 EDAC Count 715 22 3 60 eSRAM1 EDAC Count 715 22 3 61 MAC EDAC Transmitter Count 715 22 3 62 MAC EDAC Receiver Count 715 22 3 63 USB EDAC Count 716 22 3 64 CAN EDAC Count 716 22 3 65 eSRAM0 EDAC Address Register 716...

Page 12: ...5 FIIC Controller Register Bit Definitions 749 24 Fabric Interface Controller 757 24 1 Functional Description 758 24 1 1 MSS to the FPGA Fabric Interface 759 24 1 2 Configure FIC for Master or Slave Interface 759 24 2 Advanced AHB Lite Options 759 24 2 1 Configure FIC in Bypass Mode or Synchronous Pipelined Mode 759 24 2 2 Master Identity Port to the Fabric 760 24 2 3 Configure MSS Master View for...

Page 13: ...UG0331 User Guide Revision 15 0 xiii 26 Error Detection and Correction Controllers 792 26 1 Functional Description 792 26 1 1 EDAC Checksum Bits Width 793 26 2 Configuration 793 26 3 How to Use EDAC 794 ...

Page 14: ...gister Bit Assignments 98 Figure 27 IABR Register Bit Assignments 98 Figure 28 IPR Register Bit Assignments 99 Figure 29 IABR Register Bit Assignments 100 Figure 30 ACTLR Bit Assignments 103 Figure 31 CPUID Register Bit Assignments 103 Figure 32 ICSR Bit Assignments 104 Figure 33 VTOR Bit Assignments 106 Figure 34 AIRCR Bit Assignments 107 Figure 35 SCR Bit Assignments 108 Figure 36 CCR Bit Assign...

Page 15: ...50TS Device with 256 KB eNVM_0 160 Figure 83 eNVM Special Sectors for the M2S005S Device with 128 KB eNVM_0 160 Figure 84 eNVM Special Sectors for the M2S010TS M2S025TS Devices with 256 KB eNVM_0 161 Figure 85 eNVM Special Sectors for the M2S060TS Devices with 256 KB eNVM_0 161 Figure 86 eNVM Special Sectors for the M2S090TS M2S150TS Devices with 512 KB 162 Figure 87 System Builder Window 166 Figu...

Page 16: ...n USB Device Peripheral Mode 293 Figure 144 Basic USB Flow Diagram when USB Controller is in OTG Mode 295 Figure 145 LPM State Transition Diagram 296 Figure 146 MSS Configurator with USB and GPIO Macros Enabled 300 Figure 147 MSS USB Configurator with ULPI Interface Settings 301 Figure 148 MSS USB Configurator with UTMI Interface Settings 302 Figure 149 MSS GPIO Configurator with GPIO Settings for...

Page 17: ... Timing when EERR 1 486 Figure 198 Enable MMUART 486 Figure 199 MSS MMUART Configurator 487 Figure 200 MMUART Interface Signals 487 Figure 201 MMUART Driver User Guide 488 Figure 202 MMUART Sample Project 489 Figure 203 Setup to Communicate With Host PC Through MMUART Interface Block Diagram 489 Figure 204 Microcontroller Subsystem Showing SPI Peripherals 504 Figure 205 SPI Controller Block Diagra...

Page 18: ...igure 258 RTC Signals 606 Figure 259 RTC Driver User Guide 607 Figure 260 RTC Examples 608 Figure 261 MSS Showing Timer Peripherals 614 Figure 262 Timer Block Diagram 615 Figure 263 Block Diagram 32 Bit Mode 618 Figure 264 Block Diagram 64 Bit Mode 618 Figure 265 Timer Driver User Guide 619 Figure 266 Generating Sample Project 621 Figure 267 Microcontroller Subsystem Showing Watchdog Timer 629 Fig...

Page 19: ...gram for Fabric Interface Interrupt Controller 739 Figure 321 Combinational Circuit for Mapping MSS Interrupts to a MSS_INT_M2F 739 Figure 322 Configure FIIC in the MSS Configurator 741 Figure 323 FIIC Configurator 742 Figure 324 Fabric to the MSS Interrupt 743 Figure 325 MSS to Fabric Interrupt 745 Figure 326 The FIC Connection to the AHB Bus Matrix 757 Figure 327 Fabric Interface Controller Bloc...

Page 20: ...nected to the MSS 780 Figure 355 FPGA System with the MSS Slave and the Fabric Master 781 Figure 356 Fabric APB Master with MSS as Slave 782 Figure 357 APB Configuration Interface and Subsystems Connectivity with MSS Master 784 Figure 358 Configure FIC_2 in MSS Configurator 787 Figure 359 FIC_2 Configurator 788 Figure 360 FIC_2 Configuration for MSS DDR 788 Figure 361 FIC_2 Configuration for MSS D...

Page 21: ...turn Behavior 43 Table 24 Faults 43 Table 25 Fault Status and Fault Address Registers 45 Table 26 Cortex M3 Processor Instructions 47 Table 27 CMSIS Functions to Generate some Cortex M3 Processor instructions 50 Table 28 CMSIS Functions to Access the Special Registers 51 Table 29 Condition Code Suffixes 57 Table 30 Memory Access Instructions 58 Table 31 Offset Ranges 60 Table 32 Offset Ranges 63 T...

Page 22: ...AR Bit Assignments 126 Table 82 MPU_RASR Bit Assignments 127 Table 83 Example SIZE Field Values 128 Table 84 TEX C B and S Encoding 128 Table 85 Cache Policy for Memory Attribute Encoding 129 Table 86 AP Encoding 129 Table 87 Memory Region Attributes for a Microcontroller 132 Table 88 Default eNVM Remapped Mode 135 Table 89 eSRAM Remapped Mode Memory Map 135 Table 90 DDR Remap 136 Table 91 Data Pa...

Page 23: ...ble 139 AHB Bus Matrix Connectivity 211 Table 140 Fixed Priority Masters 218 Table 141 WRR Masters 218 Table 142 Pure Round Robin and Fixed Priority Arbitration Scenario for eSRAM1 220 Table 143 WRR and Fixed Priority Arbitration Scenario for eNVM_0 222 Table 144 WRR Arbitration Scenario for eSRAM_0 slave 222 Table 145 Decoding of Master Access to the Fabric Slaves 224 Table 146 Pairing of Masters...

Page 24: ...nctional Descriptions of Callback APIs 306 Table 197 SOFTRESET_REG Bit for USB Controller Soft Reset 308 Table 198 Common Register Set Description 309 Table 199 FADDR_REG 0x40043000 310 Table 200 POWER_REG 0x40043001 310 Table 201 TX_IRQ_REG 0x40043002 311 Table 202 RX_IRQ_REG 0x40043004 311 Table 203 TX_IRQ_EN_REG 0x40043006 312 Table 204 RX_IRQ_EN_REG 0x40043008 312 Table 205 USB_IRQ_REG 0x40043...

Page 25: ...REG 0x40043075 340 Table 259 ULPI_REG_CTRL 0x40043076 341 Table 260 ULPI_RAW_DATA_REG 0x40043077 Asynchronous 341 Table 261 ULPI_RAW_DATA_REG 0x40043077 Synchronous 341 Table 262 Encoded UTMI Event Signals 342 Table 263 EP_INFO_REG 0x40043078 342 Table 264 RAM_INFO_REG 0x40043079 342 Table 265 LINK_INFO_REG 0x4004307A 342 Table 266 VP_LEN_REG 0x4004307B 343 Table 267 HS_EOF1_REG 0x4004307C 343 Tab...

Page 26: ...EDAC_CNT 372 Table 316 USB_EDAC_ADR 373 Table 317 USB_SR 373 Table 318 EDAC_SR 373 Table 319 CLR_EDAC_COUNTERS 373 Table 320 MII Ports 378 Table 321 GMII Ports 378 Table 322 TBI Ports 379 Table 323 Tx Rx Descriptor 381 Table 324 PacketStartAddr 381 Table 325 Packet Size 381 Table 326 Next Descriptor 382 Table 327 TSEMAC Firmware Drivers for Initialization and Configuration 391 Table 328 TSEMAC Fir...

Page 27: ...Table 371 FIFO_RAM_ACCESS2 415 Table 372 FIFO_RAM_ACCESS3 415 Table 373 FIFO_RAM_ACCESS4 415 Table 374 FIFO_RAM_ACCESS5 415 Table 375 FIFO_RAM_ACCESS6 416 Table 376 FIFO_RAM_ACCESS7 416 Table 377 TR64 416 Table 378 TR127 416 Table 379 TR255 416 Table 380 TR511 417 Table 381 TR1K 417 Table 382 TRMAX 417 Table 383 TRMGV 417 Table 384 RBYT 417 Table 385 RPKT 418 Table 386 RFCS 418 Table 387 RMCA 418 ...

Page 28: ...N SYSREG Control Registers 451 Table 440 CAN Controller Soft Reset Bit in the SOFT_RESET_CR Register 452 Table 441 Summary of CAN Controller Registers 452 Table 442 CAN_CONFIG 454 Table 443 CAN_COMMAND 455 Table 444 TX_MSG0_CTRL_CMD 456 Table 445 TX_MSG0_ID 457 Table 446 TX_MSG0_DATA_HIGH 457 Table 447 TX_MSG0_DATA_LOW 457 Table 448 Transmit Message1 to Transmit Message31 Registers Description 458...

Page 29: ...finitions for SPI Peripheral 517 Table 497 MSS SPI APIs 524 Table 498 SYSREG Control Registers 527 Table 499 SPI Register Summary 527 Table 500 CONTROL 528 Table 501 TXRXDF_SIZE 529 Table 502 Status 530 Table 503 INT_CLEAR 531 Table 504 RX_DATA 531 Table 505 TX_DATA 531 Table 506 CLK_GEN 531 Table 507 SLAVE_SELECT 532 Table 508 CLK_MODE Example APB Clock 153 8 MHz 532 Table 509 MIS 533 Table 510 R...

Page 30: ... IOMUX CELL 14 580 Table 550 IOMUX CELL 15 580 Table 551 IOMUX CELL 16 580 Table 552 IOMUX CELL 17 581 Table 553 IOMUX CELL 18 581 Table 554 IOMUX CELL 19 581 Table 555 IOMUX CELL 20 582 Table 556 IOMUX CELL 21 582 Table 557 IOMUX CELL 22 582 Table 558 IOMUX CELL 23 582 Table 559 IOMUX CELL 24 583 Table 560 IOMUX CELL 25 583 Table 561 IOMUX CELL 26 583 Table 562 IOMUX CELL 27 584 Table 563 IOMUX C...

Page 31: ...612 The RTC_WAKEUP_CR in the SYSREG Block 613 Table 613 Timer Interface Signals 615 Table 614 Soft Reset Bit Definitions for System Peripheral 615 Table 615 MSS Timer APIs 619 Table 616 Timer Register Map 622 Table 617 TIMx_VAL 623 Table 618 TIMx_LOADVAL 623 Table 619 TIMx_BGLOADVAL 623 Table 620 TIMx_CTRL 624 Table 621 TIMx_RIS 624 Table 622 TIMx_MIS 625 Table 623 TIM64_VAL_U 625 Table 624 TIM64_...

Page 32: ...able 670 MASTER_WEIGHT0_CR 691 Table 671 MASTER_WEIGHT1_CR 692 Table 672 Programmable Weight Values 692 Table 673 SOFT_IRQ_CR 693 Table 674 SOFT_RESET_CR 693 Table 675 M3_CR 695 Table 676 FAB_IF_CR 695 Table 677 LOOPBACK_CR 696 Table 678 GPIO_SYSRESET_SEL_CR 696 Table 679 GPIN_SRC_SEL_CR 697 Table 680 MDDR_CR 697 Table 681 USB_IO_INPUT_SEL_CR 698 Table 682 PERIPH_CLK_MUX_SEL_CR 698 Table 683 WDOG_...

Page 33: ... MM0_1_2_SECURITY 718 Table 729 MM4_5_DDR_FIC_SECURITY MM4_5_FIC64_SECURITY 718 Table 730 MM3_6_7_8_SECURITY 719 Table 731 MM9_SECURITY 720 Table 732 M3_SR 721 Table 733 ETM_COUNT_LOW 721 Table 734 ETM_COUNT_HIGH 721 Table 735 DEVICE_SR 722 Table 736 ENVM_PROTECT_USER 722 Table 737 ENVM_STATUS 724 Table 738 DEVICE_VERSION 724 Table 739 MSSDDR_PLL_STATUS 724 Table 740 USB_SR 725 Table 741 ENVM_SR 7...

Page 34: ...Table 774 INTERRUPT_REASON1 753 Table 775 INTERRUPT_REASON0 754 Table 776 INTERRUPT_MODE 756 Table 777 Number of FICs Available for Use in Each Device 758 Table 778 Master Group Access to Fabric Slaves 760 Table 779 FIC Memory Regions 760 Table 780 Fabric Interface Controller Port List 762 Table 781 Address Regions and Compatible Slots for 256 MB Per Slot Option 770 Table 782 FAB_IF Register in th...

Page 35: ...ee VDD Power Up to Functional Time page 648 The test cases listed in Table 646 page 651 were updated for consistency with DS0128 IGLOO2 and SmartFusion2 Datasheet The DEVRST_N power up to functional time flow diagram Figure 283 page 651 was updated to include the POWER_ON_RESET_N signal For more information see DEVRST_N Power Up to Functional Time page 651 1 3 Revision 13 0 The following changes w...

Page 36: ...ed Functional Description page 146 chapter in Embedded NVM eNVM Controllers page 145 chapter SAR 73736 Updated Table 741 page 725 and Table 110 page 180 SAR 70182 Added Figure 82 page 160 Figure 83 page 160 Figure 84 page 161 and Figure 86 page 162 and added eNVM Pages for Special Purpose Storage page 163 SAR 66208 Updated SPI Use Models page 525 SAR 62152 Updated Table 104 page 175 Table 112 page...

Page 37: ...ration Sequence page 643 SAR 56613 Updated Table 763 page 736 for bit numbers SAR 52993 Updated Table 772 page 749 SAR 50361 Updated the introductory content of Fabric Interface Controller page 757 and added a note to Figure 336 page 766 SAR 56584 Updated Embedded NVM eNVM Controllers page 145 Embedded SRAM eSRAM Controllers page 187 AHB Bus Matrix page 210 High Performance DMA Controller page 236...

Page 38: ...4 SAR 46422 Restructured Universal Serial Bus OTG Controller page 284 SAR 47042 Restructured Ethernet MAC page 374 SAR 47043 Restructured CAN Controller page 436 SAR 50262 Restructured MMUART Peripherals page 469 SAR 50262 Restructured Serial Peripheral Interface Controller page 504 SAR 50262 Restructured Inter Integrated Circuit Peripherals page 538 SAR 50262 Restructured MSS GPIO page 562 SAR 50...

Page 39: ...Revision History UG0331 User Guide Revision 15 0 5 Added Figure 328 page 761 through Figure 336 page 766 SAR 39058 ...

Page 40: ...re pipeline core incorporating branch speculation single cycle multiplication and hardware division giving a Dhrystone benchmark of 1 25 DMIPS MHz A nested vectored interrupt controller NVIC that closely integrates with the processor core to achieve low latency interrupt processing A memory protection unit MPU is included This facilitates the protected memory regions creation and setting access ri...

Page 41: ...essor NVIC Cortex M3 Processor SysTick Timer Cortex M3 Processor Debug Subsystem Data Watch Point DWP and Trace Instrumentation Trace Macrocell Embedded Trace Macrocell Note The Cortex M3 operating frequency is dependent on device speed grade up to 166 MHz Refer to SmartFusion2 Specifications MSS Clock Frequency section from DS0128 IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet for more informati...

Page 42: ...nd reset Non maskable exception 2 2 Non maskable interrupt NMI watchdog timeout interrupt HardFault 3 1 Hard fault interrupt all fault conditions if the corresponding fault handler is not enabled Memory management exception 4 Configurable Memory management interrupt memory management fault MPU violation or access to illegal locations Bus fault exception 5 Configurable Bus fault interrupt bus error...

Page 43: ...INTISR 18 ENVM_INT1 ENVMTOAHB1 Asserted on an eNVM_1 basis at the completion of ERASE_PAGE PROGRAM ECC ERROR etc INTISR 19 COMM_BLK_INTR COMBLK Communication block interrupt INTISR 20 USB_MC_INT USB CPU interrupts INTISR 21 USB_DMA_INT USB Core s DMA engine performs data transfer between endpoint memories and system memory via AHB master port DMA controller interrupt INTISR 22 MSSDDR_PLL_LOCK_INT ...

Page 44: ...transfer with error Once asserted it remains asserted until cleared by means of writing 1 to the bit in the control register of the Descriptor N 0 1 2 3 If HPDMA completes more than one descriptor with errors before the interrupt is serviced then this bit remains asserted until all the descriptors have had Clr_D N _Xfr_err_int written to 1 INTISR 29 ECCINTR SYSREG It is asserted when an ECC error ...

Page 45: ...44 F2H_INTERRUPT 10 FPGA fabric Interrupt from the FPGA fabric INTISR 45 F2H_INTERRUPT 11 FPGA fabric Interrupt from the FPGA fabric INTISR 46 F2H_INTERRUPT 12 FPGA fabric Interrupt from the FPGA fabric INTISR 47 F2H_INTERRUPT 13 FPGA fabric Interrupt from the FPGA fabric INTISR 48 F2H_INTERRUPT 14 FPGA fabric Interrupt from the FPGA fabric INTISR 49 F2H_INTERRUPT 15 FPGA fabric Interrupt from the...

Page 46: ...ing debug Interfaces SWJ DP JTAG is the industry standard interface used to download and debug programs on a target processor as well as for other functions It offers access to all of the Cortex M3 processor CoreSight debug capabilities SW DP The serial wire debug SWD mode is an alternative to the standard JTAG interface SWD uses two pins to provide the same debug functionality as JTAG with no per...

Page 47: ...executed instruction continuously for a selected portion of your application Trace data can be useful for debugging issues and collecting statistics Locating errors that have irregular symptoms Analyzing dynamic system behavior Optimizing performance bottlenecks Counting code coverage statistics Trace results are generated in the form of packets which can be of various lengths The trace components...

Page 48: ...ng details for JTAG SWD and ETM modes of the debug section For more details on pin information refer to the DS0115 SmartFusion2 Pin Descriptions Datasheet Table 3 Signal Multiplexing FPGA Pin JTAG Mode SWD Mode ETM Mode JTAG_TMS M3_TMS M3_SWDIO TMS SWDIO SWDIO JTAG_TCK M3_TCK TCK SWCLK SWCLK Cortex M 3 Processor Core AHB Bus Matrix ETM DWT PC Sampler Interrupt Trace 4 Watch points ETM Trigger ITM ...

Page 49: ...FO queue of 24 bytes and ETM outputs 8 bits of data at a time at the core clock speed This output is compatible with the AMBA trace bus ATB The ETM trace is supported by tools like Keil Trace IAR Trace Greenhills software trace and others The ETM provides the following features Tracing of 16 bit and 32 bit thumb instructions Four EmbeddedICE watchpoint inputs A Trace Start Stop block with Embedded...

Page 50: ...have been updated in Libero SoC In addition timing arcs for the Cortex M3 Embedded Trace Macrocell ETM have been added DEEPSLEEP Out No Signal is asserted when the Cortex M3 processor is in sleep now or sleep on exit mode when the SLEEPDEEP bit of the system control register is set SLEEPHOLDREQn In No Request to extend Cortex M3 processor sleep state Signal is asserted when SLEEPING signal is High...

Page 51: ... when in SLEEPING or SLEEPDEEP mode SLEEPING and SLEEPDEEP signals are available at the FPGA fabric interface Sleep mode extension handshake signals are available at the FPGA fabric interface System power management options can be configured as shown in Figure 3 page 16 2 7 1 5 Trace Port Interface Unit TPIU Configuration TRACECLK TRACEDATA 3 0 can be exposed to the FPGA fabric TACECLK can be conf...

Page 52: ...lements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities The Cortex M3 processor implements a version of the Thumb instruction set based on Thumb 2 technology ensuring high code density and reduced program memory requirements The Cortex M3 processor instruction set provides the exceptional performance expect...

Page 53: ...e a Serial Wire Viewer SWV can export a stream of software generated messages data trace and profiling information through a single pin The optional Embedded Trace Macrocell ETM delivers unrivaled instruction trace capture in an area far smaller than traditional trace units enabling many low cost MCUs to implement full instruction trace for the first time The optional Flash Patch and Breakpoint Un...

Page 54: ...te application software The processor enters Thread mode when it comes out of reset Handler mode Used to handle exceptions The processor returns to Thread mode when it has finished all exception processing The privilege levels for software execution are Unprivileged The software has limited access to the MSR and MRS instructions and cannot use the CPS instruction cannot access the system timer NVI...

Page 55: ...ck Handler Exception handlers Always privileged Main stack Table 8 Core Register Set Summary Name Type1 Required privilege2 Reset value Description R0 R12 RW Either Unknown General Purpose Registers MSP RW Privileged See description Stack Pointer PSP RW Either Unknown Stack Pointer LR RW Either 0xFFFFFFFF Link Register PC RW Either See description Program Counter PSR RW Privileged Unknown Program ...

Page 56: ...tatus Register The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These registers are mutually exclusive bitfields in the 32 bit PSR The bit assignments are shown in the following figure Figure 6 Program Status Register EPSR RO Privileged 0x01000000 Execution Program Status Register PRIMASK...

Page 57: ...s See the register summary in the following table for its attributes The following table lists the bit assignments 3 5 1 3 7 Interrupt Program Status Register The IPSR contains the exception type number of the current Interrupt Service Routine ISR See the register summary in Table 8 page 21 for its attributes The following table lists the bit assignments Table 9 PSR Combinations and Attributes Reg...

Page 58: ...he MRS instruction always return zero Attempts to write the EPSR using the MSR instruction are ignored 8 0 ISR_NUMBER This is the number of the current exception 0 Thread mode 1 Reserved 2 NMI 3 HardFault 4 MemManage 5 BusFault 6 UsageFault 7 10 Reserved 11 SVCall 12 Reserved for Debug 13 Reserved 14 PendSV 15 SysTick 16 IRQ0 255 IRQ239 See Exception Types page 37 for more information Table 12 EPS...

Page 59: ... POP PC restoration from the stacked xPSR value on an exception return bit 0 of the vector value on an exception entry or reset Attempting to execute instructions when the T bit is 0 results in a fault or lockup See Lockup page 45 for more information The T bit can be modified both by software using the mechanisms described in this section and directly by the debugger 3 5 1 3 9 Exception Mask Regi...

Page 60: ...ure 9 Base Priority Mask Register The following table lists the big assignments for MSR or MRS access Figure 8 Fault Mask Register Table 14 FAULT Register Bit Assignments Bits Name Function 31 1 Reserved 0 FAULTMASK 0 no effect 1 prevents the activation of all exceptions except for NMI Table 15 BASEPRI Register Bit Assignments Bits Name Function 31 8 Reserved 7 0 BASEPRI1 1 This field is similar t...

Page 61: ...el and exception handlers use the main stack By default Thread mode uses the MSP To switch the stack pointer used in Thread mode to the PSP either use the MSR instruction to set the Active stack pointer bit to 1 see MSR page 92 perform an exception return to Thread mode with the appropriate EXC_RETURN value see Table 23 page 43 Note When changing the stack pointer software must use an ISB instruct...

Page 62: ...r SmartFusion2 SoC FPGA MSS uses only little endian Refer to Memory Regions Types and Attributes page 29 3 5 1 6 The Cortex Microcontroller Software Interface Standard For a Cortex M3 processor system the Cortex Microcontroller Software Interface Standard CMSIS defines a common way to access peripheral registers define exception vectors the names of the registers of the core peripherals the core e...

Page 63: ...e memory type and attributes determine the behavior of accesses to the region The memory types are Normal The processor can re order transactions for efficiency or perform speculative reads Device The processor preserves transaction order relative to other transactions to Device or Strongly ordered memory Strongly ordered The processor preserves transaction order relative to all other transactions...

Page 64: ...ory system does guarantee some ordering of accesses to Device and Strongly ordered memory The following figure shows the ordering of the memory accesses caused by two instructions A1 and A2 if A1 occurs before A2 in program order Figure 12 Memory Ordering Restrictions Where Means that the memory system does not guarantee the ordering of the accesses Means that accesses are observed in program orde...

Page 65: ...ove efficiency providing this does not affect the behavior of the instruction sequence the processor has multiple bus interfaces memory or devices in the memory map have different wait states some memory accesses are buffered or speculative 0xE0000000 0xE00FFFFF Private Peripheral Bus Strongly ordered XN This region includes the NVIC System timer and system control block 0xE0100000 0xFFFFFFFF Vend...

Page 66: ...he memory map has two 32MB alias regions that map to two 1MB bit band regions accesses to the 32MB SRAM alias region map to the 1MB SRAM bit band region as detailed in Table 19 page 32 accesses to the 32MB peripheral alias region map to the 1MB peripheral bit band region as detailed in Table 20 page 32 Notes A word access to the SRAM or peripheral bit band alias regions maps to a single bit in the...

Page 67: ...as word at 0x2200001C maps to bit 7 of the bit band byte at 0x20000000 0x2200001C 0x22000000 0 32 7 4 Figure 13 Bit band Mapping 3 5 2 5 1 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit band region Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit band region Writing a value...

Page 68: ...ant big endian format Figure 14 Byte Invariant Big Endian Format 3 5 2 6 2 Little Endian format In little endian format the processor stores the least significant byte of a word at the lowest numbered byte and the most significant byte at the highest numbered byte Cortex M3 processor configured for SmartFusion2 SoC FPGA MSS uses only little endian The following figure illustrates the little endian...

Page 69: ...try the read modify write sequence Software can use the synchronization primitives to implement a semaphores as follows 1 Use a Load Exclusive instruction to read from the semaphore address to check whether the semaphore is free 2 If the semaphore is free use a Store Exclusive to write the claim value to the semaphore address 3 If the returned status bit from step2 indicates that the Store Exclusi...

Page 70: ...Reset Reset is invoked on power up or a warm reset The exception model treats reset as a special form of exception When reset is asserted the operation of the processor stops potentially at any point in an instruction When reset is deasserted execution restarts from the address provided by the reset entry in the vector table Execution restarts as privileged execution in Thread mode NMI A Non Maska...

Page 71: ...tion an error on exception return The following can cause a UsageFault when the core is configured to report them an unaligned address on word and halfword memory access division by zero SVCall A supervisor call SVC is an exception that is triggered by the SVC instruction In an OS environment applications can use SVC instructions to access OS kernel functions and device drivers PendSV PendSV is an...

Page 72: ...hat are handled by system handlers Table 22 Properties of the Different Exception Types Exception number1 1 To simplify the software layer the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts The IPSR returns the Exception number see Interrupt Program Status Register page 23 IRQ number1 Exception type Priority Vector address or offset2 2 See Vecto...

Page 73: ...Fault and NMI If software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information about configuring exception priorities see System Handler Priority Registers page 110 and Interrupt Priority Registers page 99 Note Configurable priority values are in the range 0 255 This means that the Reset HardFault and NMI exceptions with fixed nega...

Page 74: ...can preempt the exception handler if its priority is higher than the priority of the exception being handled See Interrupt Priority Grouping page 41 for more information about preemption by an interrupt When one exception preempts another the exceptions are called nested exceptions See Exception Entry page 41 more information Return This occurs when the exception handler is completed and there is ...

Page 75: ... complete the processor starts executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred If no higher priority exception occurs during exception entry the processor starts executing the exception handler and automatically...

Page 76: ... privilege violation or an attempt to access an unmanaged region 3 5 4 1 Fault Types The following table shows the types of fault the handler used for the fault the corresponding fault status register and the register bit that indicates that the fault has occurred See Configurable Fault Status Register page 113 for more information about the fault status registers Table 23 Exception Return Behavio...

Page 77: ...This is because the handler for the new fault cannot preempt the currently executing fault handler An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception A fault occurs and the handler for that fault is not enabled If a BusFault occurs during a stack push when entering a BusFault handler the BusFault does not escalate to a HardFaul...

Page 78: ...n Sleep mode stops the processor clock Deep sleep mode stops the system clock and switches off the PLL and flash memory The SLEEPDEEP bit of the SCR selects which Sleep mode is used refer to System Control Register page 108 This section describes the mechanisms for entering Sleep mode and the conditions for waking up from Sleep mode 3 5 5 1 Entering Sleep Mode This section describes the mechanisms...

Page 79: ...an interrupt handler To achieve this set the PRIMASK bit to 1 and the FAULTMASK bit to 0 If an interrupt arrives that is enabled and has a higher priority than current exception priority the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to zero For more information about PRIMASK and FAULTMASK see Exception Mask Registers page 25 3 5 5 2 2 Wakeup fro...

Page 80: ...nstruction set The following table lists the supported instructions In the following table angle brackets enclose alternative forms of the operand braces enclose optional operands the Operands column is not exhaustive Op2 is a flexible second operand that can be either a register or a constant most instructions can use an optional condition code suffix For more information on the instructions and ...

Page 81: ...t Rn offset Load Register Exclusive LDREXB Rt Rn Load Register Exclusive with Byte LDREXH Rt Rn Load Register Exclusive with Halfword LDRH LDRHT Rt Rn offset Load Register with Halfword LDRSB LDRSBT Rt Rn offset Load Register with Signed Byte LDRSH LDRSHT Rt Rn offset Load Register with Signed Halfword LDRT Rt Rn offset Load Register with word LSL LSLS Rd Rm Rs n Logical Shift Left N Z C LSR LSRS ...

Page 82: ...esult SMULL RdLo RdHi Rn Rm Signed Multiply 32 x 32 64 bit result SSAT Rd n Rm shift s Signed Saturate Q STM Rn reglist Store Multiple registers increment after STMDB STMEA Rn reglist Store Multiple registers decrement before STMFD STMIA Rn reglist Store Multiple registers increment after STR Rt Rn offset Store Register word STRB STRBT Rt Rn offset Store Register byte STRD Rt Rt2 Rn offset Store R...

Page 83: ...Rd Rn Rm Unsigned Divide UMLAL RdLo RdHi Rn Rm Unsigned Multiply with Accumulate 32 x 32 64 64 bit result UMULL RdLo RdHi Rn Rm Unsigned Multiply 32 x 32 64 bit result USAT Rd n Rm shift s Unsigned Saturate Q UXTB Rd Rm ROR n Zero extend a Byte UXTH Rd Rm ROR n Zero extend a Halfword WFE Wait for Event WFI Wait for Interrupt Table 27 CMSIS Functions to Generate some Cortex M3 Processor instruction...

Page 84: ...X LDM LDR or POP instruction must be 1 for correct execution because this bit indicates the required instruction set and the Cortex M3 processor only supports Thumb instructions 3 6 3 3 Flexible Second Operand Many general data processing instructions have a flexible second operand This is shown as Operand2 in the descriptions of the syntax of each instruction Operand2 can be a constant or a regis...

Page 85: ...uction uses the value in Rm If you specify a shift the shift is applied to the value in Rm and the resulting 32 bit value is used by the instruction However the contents in the register Rm remains unchanged Specifying a register with shift also updates the carry flag when used with certain instructions For information on the shift operations and how they affect the carry flag refer to Shift Operat...

Page 86: ... Figure 18 ASR 3 3 6 3 4 2 LSR Logical shift right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result And it sets the left hand n bits of the result to 0 See the following figure You can use the LSR n operation to divide the value in the register Rm by 2n if the value is regarded as an unsigned integer When the instructio...

Page 87: ... not affect the carry flag when used with LSL 0 If n is 32 or more then all the bits in the result are cleared to 0 If n is 33 or more and the carry flag is updated it is updated to 0 Figure 20 LSL 3 6 3 4 4 ROR Rotate right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result And it moves the right hand n bits of the regis...

Page 88: ...are aligned To trap accidental generation of unaligned accesses use the UNALIGN_TRP bit in the Configuration and Control Register refer to Configuration and Control Register page 109 3 6 3 6 PC relative Expressions A PC relative expression or label is a symbol that represents the address of an instruction or literal data It is represented in the instruction as the PC value plus or minus a numeric ...

Page 89: ...se Z Set to 1 when the result of the operation was zero cleared to 0 otherwise C Set to 1 when the operation resulted in a carry cleared to 0 otherwise V Set to 1 when the operation caused overflow cleared to 0 otherwise For more information about the APSR refer to Program Status Register page 22 A carry occurs If the result of an addition is greater than or equal to 232 If the result of a subtrac...

Page 90: ...reater than R1 and R2 is greater than R3 Example 2 Compare and update value CMP R0 R1 Compare R0 and R1 setting flags ITT GT Skip next two instructions unless GT condition holds CMPGT R2 R3 If greater than compare R2 and R3 setting flags MOVGT R4 R5 If still greater than do R4 R5 Table 29 Condition Code Suffixes Suffix Flags Meaning EQ Z 1 Equal NE Z 0 Not equal CS or HS C 1 Higher or same unsigne...

Page 91: ...n BCS W label creates a 32 bit instruction even for a short branch ADDS W R0 R0 R1 creates a 32 bit instruction even though the same operation can be done by a 16 bit instruction 3 6 4 Memory Access Instructions The following table provides memory access instructions Table 30 Memory Access Instructions Mnemonic Brief Description See ADR Generate PC relative address ADR page 59 CLREX Clear Exclusiv...

Page 92: ...r to generate addresses that are not word aligned See Instruction Width Selection page 58 3 6 4 1 3 Restrictions Rd must not be SP and must not be PC 3 6 4 1 4 Condition flags This instruction does not change the flags Examples ADR R1 TextMessage Write address value of a location labelled as TextMessage to R1 3 6 4 2 LDR and STR Immediate Offset Load and Store with immediate offset pre indexed imm...

Page 93: ...from the register Rn is used as the address for the memory access The offset value is added to or subtracted from the address and written back into the register Rn The assembly language syntax for this mode is Rn offset The value to load or store can be a byte halfword word or two words Bytes and halfwords can either be signed or unsigned Refer to Address Alignment page 55 The following table list...

Page 94: ...gister offset 3 6 4 3 1 Syntax op type cond Rt Rn Rm LSL n where op is either LDR load register or STR store register type is one of B unsigned byte zero extend to 32 bits on loads SB signed byte sign extend to 32 bits LDR only H unsigned halfword zero extend to 32 bits on loads SH signed halfword sign extend to 32 bits LDR only omit for word cond is an optional condition code refer to Conditional...

Page 95: ...d Load and Store with unprivileged access 3 6 4 4 1 Syntax op type T cond Rt Rn offset immediate offset where op is either LDR load register or STR store register type is one of B unsigned byte zero extend to 32 bits on loads SB signed byte sign extend to 32 bits LDR only H unsigned halfword zero extend to 32 bits on loads SH signed halfword sign extend to 32 bits LDR only omit for word cond is an...

Page 96: ...gn extend to 32 bits omit for word cond is an optional condition code see Conditional Execution page 55 Rt is the register to load or store Rt2 is the second register to load or store label is a PC relative expression See PC relative Expressions page 55 3 6 4 5 2 Operation LDR loads a register with a value from a PC relative memory address The memory address is specified by a label or by an offset...

Page 97: ...n optional condition code see Conditional Execution page 55 Rn is the register on which the memory addresses are based is an optional writeback suffix If is present the final address that is loaded from or stored to is written back into Rn reglist is a list of one or more registers to be loaded or stored enclosed in braces It can contain register ranges It must be comma separated if it contains mo...

Page 98: ...ed to the PC must be 1 for correct execution and a branch occurs to this halfword aligned address if the instruction is conditional it must be the last instruction in the IT block 3 6 4 6 4 Condition Flags These instructions do not change the flags Examples LDM R8 R0 R2 R9 LDMIA is a synonym for LDM TMDB R1 R3 R6 R11 R12 Incorrect Examples STM R5 R5 R4 R9 Value stored for R5 is unpredictable LDM R...

Page 99: ...ction is conditional it must be the last instruction in the IT block 3 6 4 7 4 Condition Flags These instructions do not change the flags Examples PUSH R0 R4 R7 Push R0 R4 R5 R6 R7 onto the stack PUSH R2 LR Push R2 and the link register onto the stack POP R0 R6 PC Pop r0 r6 and PC from the stack then branch to the new PC 3 6 4 8 LDREX and STREX Load and Store Register Exclusive 3 6 4 8 1 Syntax LD...

Page 100: ...sive instruction is unpredictable 3 6 4 8 3 Restrictions In these instructions do not use PC do not use SP for Rd and Rt for STREX Rd must be different from both Rt and Rn the value of offset must be a multiple of four in the range 0 1020 3 6 4 8 4 Condition Flags These instructions do not change the flags Examples MOV R1 0x1 Initialize the lock taken value try LDREX R0 LockAddr Load the lock valu...

Page 101: ...1 LSR Logical Shift Right ASR LSL LSR ROR and RRX page 71 MOV Move MOV and MVN page 73 MOVT Move Top MOVT page 75 MOVW Move 16 bit constant MOV and MVN page 73 MVN Move NOT MOV and MVN on page 73 ORN Logical OR NOT AND ORR EOR BIC and ORN page 70 ORR Logical OR AND ORR EOR BIC and ORN page 70 RBIT Reverse Bits REV REV16 REVSH and RBIT page 75 REV Reverse byte order in a word REV REV16 REVSH and RB...

Page 102: ...alue in Rn If the carry flag is clear the result is reduced by one The RSB instruction subtracts the value in Rn from the value of Operand2 This is useful because of the wide range of options for Operand2 Use ADC and SBC to synthesize multiword arithmetic see Multiword Arithmetic Examples page 70 See also ADR page 59 Note ADDW is equivalent to the ADD syntax that uses the imm12 operand SUBW is equ...

Page 103: ...integer contained in R2 and R3 to another 64 bit integer contained in R0 and R1 and place the result in R4 and R5 Example 4 64 bit addition ADDS R4 R0 R2 add the least significant words ADC R5 R1 R3 add the most significant words with carry Multiword values do not have to use consecutive registers The following example shows instructions that subtract a 96 bit integer contained in R9 R1 and R11 fr...

Page 104: ...the N and Z flags according to the result can update the C flag during the calculation of Operand2 see Flexible Second Operand page 51 do not affect the V flag Examples AND R9 R2 0xFF00 ORREQ R2 R0 R5 ANDS R9 R8 0x19 EORS R7 R11 0x18181818 BIC R0 R1 0xab ORN R7 R11 R14 ROR 4 ORNS R7 R11 R14 ASR 32 3 6 5 3 ASR LSL LSR ROR and RRX Arithmetic Shift Right Logical Shift Left Logical Shift Right Rotate ...

Page 105: ...ns Do not use SP and do not use PC 3 6 5 3 4 Condition Flags If S is specified these instructions update the N and Z flags according to the result the C flag is updated to the last bit shifted out except when the shift length is 0 see Shift Operations page 52 Examples ASR R7 R8 9 Arithmetic shift right by 9 bits LSLS R1 R2 3 Logical shift left by 3 bits with flag update LSR R4 R5 6 Logical shift r...

Page 106: ...lt but do not write the result to a register The CMP instruction subtracts the value of Operand2 from the value in Rn This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Operand2 to the value in Rn This is the same as an ADDS instruction except that the result is discarded 3 6 5 5 3 Restrictions In these instructions do not use PC Operan...

Page 107: ... S cond Rd Rm Rs See ASR LSL LSR ROR and RRX page 71 The MVN instruction takes the value of Operand2 performs a bitwise logical NOT operation on the value and places the result into Rd Note The MOVW instruction provides the same function as MOV but is restricted to using the imm16 operand 3 6 5 6 3 Restrictions You can use SP and PC only in the MOV instruction with the following restrictions the s...

Page 108: ... REVSH and RBIT Reverse bytes and Reverse bits 3 6 5 8 1 Syntax op cond Rd Rn where op is any of REV Reverse byte order in a word REV16 Reverse byte order in each halfword independently REVSH Reverse byte order in the bottom halfword and sign extend to 32 bits RBIT Reverse the bit order in a 32 bit word cond is an optional condition code see Conditional Execution page 55 Rd is the destination regi...

Page 109: ...ND operation on the value in Rn and the value of Operand2 This is the same as the ANDS instruction except that it discards the result To test whether a bit of Rn is 0 or 1 use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0 The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2 This is the ...

Page 110: ...east significant 32 bits of the result in Rd The MLA instruction multiplies the values from Rn and Rm adds the value from Ra and places the least significant 32 bits of the result in Rd The MLS instruction multiplies the values from Rn and Rm subtracts the product from the value from Ra and places the least significant 32 bits of the result in Rd The results of these instructions do not depend on ...

Page 111: ...MLAL Signed Long Multiply with Accumulate cond is an optional condition code see Conditional Execution page 55 RdHi RdLo are the destination registers For UMLAL and SMLAL they also hold the accumulating value Rn Rm are registers holding the operands 3 6 6 2 2 Operation The UMULL instruction interprets the values from Rn and Rm as unsigned integers It multiplies these integers and places the least ...

Page 112: ...ion register is Rn Rn is the register holding the value to be divided Rm is a register holding the divisor 3 6 6 3 2 Operation SDIV performs a signed integer division of the value in Rn by the value in Rm UDIV performs an unsigned integer division of the value in Rn by the value in Rm For both instructions if the value in Rn is not divisible by the value in Rm the result is rounded towards zero 3 ...

Page 113: ... 2n 1 the result returned is 2n 1 if the value to be saturated is greater than 2n 1 1 the result returned is 2n 1 1 otherwise the result returned is the same as the value to be saturated For unsigned n bit saturation using USAT this means that if the value to be saturated is less than 0 the result returned is 0 if the value to be saturated is greater than 2n 1 the result returned is 2n 1 otherwise...

Page 114: ...copies a bitfield into one register from another register It replaces width bits in Rd starting at the low bit position lsb with width bits from Rn starting at bit 0 Other bits in Rd are unchanged 3 6 8 1 3 Restrictions Do not use SP and do not use PC 3 6 8 1 4 Condition Flags These instructions do not affect the flags Examples BFC R4 8 12 Clear bit 8 to bit 19 12 bits of R4 to 0 BFI R9 R2 8 12 Re...

Page 115: ...ictions Do not use SP and do not use PC 3 6 8 2 4 Condition Flags These instructions do not affect the flags Examples SBFX R0 R1 20 4 Extract bit 20 to bit 23 4 bits from R1 and sign extend to 32 bits and then write the result to R0 UBFX R8 R11 9 10 Extract bit 9 to bit 18 10 bits from R11 and zero extend to 32 bits and then write the result to R8 3 6 8 3 SXT and UXT Sign extend and Zero extend 3 ...

Page 116: ... then sign extend to 32 bits and write the result to R4 UXTB R3 R10 Extract lowest byte of the value in R10 and zero extend it and write the result to R3 3 6 9 Branch and Control Instructions The following table lists the branch and control instructions 3 6 9 1 B BL BX and BLX Branch instructions 3 6 9 1 1 Syntax B cond label BL cond label BX cond Rm BLX cond Rm where B is branch immediate Table 3...

Page 117: ... The following table lists the ranges for the various branch instructions You may have to use the W suffix to get the maximum branch range See Instruction Width Selection page 58 3 6 9 1 3 Restrictions The restrictions are do not use PC in the BLX instruction for BX and BLX bit 0 of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit 0 to 0 when any...

Page 118: ...dition code flags and to reduce the number of instructions CBZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BEQ label CBNZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BNE label 3 6 9 2 3 Restrictions The restrictions are Rn must be in the range of R0 to R7 the branch destination must be within 4 to 130 bytes after the instruc...

Page 119: ...T block is always executed even if its condition fails Exceptions can be taken between an IT instruction and the corresponding IT block or within an IT block Such an exception results in entry to the appropriate exception handler with suitable return information in LR and stacked PSR Instructions designed for use for exception returns can be used as normal to return from the exception and executio...

Page 120: ... R0 R1 Syntax error no condition code used in IT block 3 6 9 4 TBB and TBH Table Branch Byte and Table Branch Halfword 3 6 9 4 1 Syntax TBB Rn Rm TBH Rn Rm LSL 1 where Rn is the register containing the address of the table of branch lengths If Rn is PC then the address of the table is the address of the byte immediately following the TBB or TBH instruction Rm is the index register This contains an...

Page 121: ...ddress of the branch table Case1 an instruction sequence follows Case2 an instruction sequence follows Case3 an instruction sequence follows BranchTable_Byte DCB 0 Case1 offset calculation DCB Case2 Case1 2 Case2 offset calculation DCB Case3 Case1 2 Case3 offset calculation TBH PC R1 LSL 1 R1 is the index PC is used as base of the branch table BranchTable_H DCI CaseA BranchTable_H 2 CaseA offset c...

Page 122: ...10 1 3 Condition Flags This instruction does not change the flags Examples BKPT 0x3 Breakpoint with immediate value set to 0x3 debugger can extract the immediate value by locating it using the PC Note ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose other than Semi hosting 3 6 10 2 CPS Change Processor State Table 38 Miscellaneous Instructi...

Page 123: ...tion does not change the condition flags Examples CPSID i Disable interrupts and configurable fault handlers set PRIMASK CPSID f Disable interrupts and all fault handlers set FAULTMASK CPSIE i Enable interrupts and configurable fault handlers clear PRIMASK CPSIE f Enable interrupts and fault handlers clear FAULTMASK 3 6 10 3 DMB Data Memory Barrier 3 6 10 3 1 Syntax DMB cond where cond is an optio...

Page 124: ... ISB cond where cond is an optional condition code see Conditional Execution page 55 3 6 10 5 2 Operation ISB acts as an instruction synchronization barrier It flushes the pipeline of the processor so that all instructions following the ISB are fetched from cache or memory again after the ISB instruction has been completed 3 6 10 5 3 Condition Flags This instruction does not change the flags Examp...

Page 125: ...PSR MSP PSP PRIMASK BASEPRI BASEPRI_MAX FAULTMASK or CONTROL Note The processor ignores MSR writes to the EPSR and IPSR fields 3 6 10 7 2 Operation The register access operation in MSR depends on the privilege level Unprivileged software can only access the APSR see Table 10 page 23 Privileged software can access all special registers In unprivileged software writes to unallocated or execution sta...

Page 126: ...l processors within a multiprocessor system It also sets the local event register to 1 see Power Management page 45 3 6 10 9 3 Condition Flags This instruction does not change the flags Examples SEV Send Event 3 6 10 10 SVC Supervisor Call 3 6 10 10 1Syntax SVC cond imm where cond is an optional condition code see Conditional Execution page 55 imm is an expression evaluating to an integer in the r...

Page 127: ... a peripheral or another processor in a multiprocessor system using the SEV instruction If the event register is 1 WFE clears it to 0 and returns immediately For more information see Power Management page 45 Condition flags This instruction does not change the flags Examples WFE Wait for event 3 6 10 12 WFI Wait for Interrupt 3 6 10 12 1Syntax WFI cond where cond is an optional condition code see ...

Page 128: ...rupt signals Dynamic reprioritization of interrupts Grouping of priority values into group priority and subpriority fields Interrupt tail chaining An external Non maskable interrupt NMI The processor automatically stacks its state on exception entry and unstacks this state on exception exit with no instruction overhead This provides low latency exception handling The hardware implementation of the...

Page 129: ...x00000000 Interrupt Priority Registers page 99 0xE000EF00 STIR WO Configurable1 0x00000000 Software Trigger Interrupt Register page 100 1 See the register description for more information Table 41 CMSIS Access NVIC Functions CMSIS Function Description void NVIC_EnableIRQ IRQn_Type IRQn 1 1 The input parameter IRQn is the IRQ number see Table 22 on page 34 for more information Enables an interrupt ...

Page 130: ...The bit assignments are Figure 24 ICER Register Bit Assignments 3 7 1 5 Interrupt Set pending Registers The NVIC_ISPR0 NVIC_ISPR7 registers force interrupts into the pending state and show which interrupts are pending See the register summary in Table 40 page 95 for the register attributes The bit assignments are Figure 25 ISPR Register Bit Assignments Table 42 NVIC_ISER Bit Assignments Bits Name ...

Page 131: ...bit does not affect the active state of the corresponding interrupt 3 7 1 7 Interrupt Active Bit Registers The NVIC_IABR0 NVIC_IABR7 registers indicate which interrupts are active See the register summary in Table 40 page 95 for the register attributes The bit assignments are Figure 27 IABR Register Bit Assignments Table 44 NVIC_ISPR Bit Assignments Bits Name Function 31 0 SETPEND Interrupt set pe...

Page 132: ...onding IPRn number see the preceding table n is given by n m DIV 4 the byte offset of the required Priority field in this register is m MOD 4 where byte offset 0 refers to register bits 7 0 byte offset 1 refers to register bits 15 8 byte offset 2 refers to register bits 23 16 byte offset 3 refers to register bits 31 24 Table 46 NVIC_IABR Bit Assignments Bits Name Function 31 0 ACTIVE Interrupt act...

Page 133: ... signal is not deasserted before the processor returns from the ISR the interrupt becomes pending again and the processor must execute its ISR again This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing See reference required for details of which interrupts are level sensitive and which are pulsed 3 7 1 10 1 Hardware and Software Control of Interr...

Page 134: ...mming VTOR to relocate the vector table ensure the vector table entries of the new vector table are setup for fault handlers NMI and all enabled exception like interrupts For more information see Vector Table Offset Register page 106 3 7 1 11 1 NVIC programming hints Software uses the CPSIE I and CPSID I instructions to enable and disable interrupts The CMSIS provides the following intrinsic funct...

Page 135: ...0000000 Vector Table Offset Register page 106 0xE000ED0C AIRCR RWa Privileged 0xFA050000 Application Interrupt and Reset Control Register page 106 0xE000ED10 SCR RW Privileged 0x00000000 System Control Register page 108 0xE000ED14 CCR RW Privileged 0x00000200 Configuration and Control Register page 109 0xE000ED18 SHPR1 RW Privileged 0x00000000 System Handler Priority Registers page 110 0xE000ED1C ...

Page 136: ...y map accesses This causes all BusFaults to be precise BusFaults but decreases performance because any store to memory must complete before the processor can execute the next instruction This bit only affects write buffers implemented in the Cortex M3 processor 0 DISMCYCINT When set to 1 disables interruption of load multiple and store multiple instructions This increases the interrupt latency of ...

Page 137: ...the p value in the rnpn product revision identifier 0x0 Patch 0 Table 53 ICSR Bit Assignments Bits Name Type Function 31 NMIPENDSET RW NMI set pending bit Write 0 no effect 1 changes NMI exception state to pending Read 0 NMI exception is not pending 1 NMI exception is pending Because NMI is the highest priority exception normally the processor enter the NMI exception handler as soon as it register...

Page 138: ...ocessor is not in Debug 22 ISRPENDING RO Interrupt pending flag excluding NMI and Faults 0 interrupt not pending 1 interrupt pending 21 18 Reserved 17 12 VECTPENDIN G RO Indicates the exception number of the highest priority pending enabled exception 0 no pending exceptions Nonzero the exception number of the highest priority pending enabled exception The value indicated by this field includes the...

Page 139: ...of two For example if you require 21 interrupts the alignment must be on a 64 word boundary because the required table size is 37 words and the next power of two is 64 Table alignment requirements mean that bits 6 0 of the table offset are always zero 3 7 2 5 Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model endian status for data...

Page 140: ... during reset 14 11 Reserved 10 8 PRIGROUP R W Interrupt priority grouping field This field determines the split of group priority from subpriority see Binary Point on page 102 7 3 Reserved 2 SYSRESETREQ WO System reset request 0 no system reset request 1 asserts a signal to the outer system that requests a reset This is intended to force a large system reset of all major components except for deb...

Page 141: ...able 57 SCR Bit Assignments Bits Name Function 31 5 Reserved 4 SEVONPEND Send Event on Pending bit 0 only enabled interrupts or events can wakeup the processor disabled interrupts are excluded 1 enabled events and all interrupts including disabled interrupts can wakeup the processor When an event or interrupt enters pending state the event signal wakes up the processor from WFE If the processor is...

Page 142: ... Reserved Table 58 CCR Bit Assignments Bits Name Function 31 10 Reserved 9 STKALIGN Indicates stack alignment on exception entry 0 4 byte aligned 1 8 byte aligned On exception entry the processor uses bit 9 of the stacked PSR to indicate the stack alignment On return from the exception it uses this stacked bit to restore the correct stack alignment 8 BFHFNMIGN Enables handlers with priority 1 or 2...

Page 143: ...ned access traps 0 do not trap unaligned halfword and word accesses 1 trap unaligned halfword and word accesses If this bit is set to 1 an unaligned access generates a UsageFault Unaligned LDM STM LDRD and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1 2 Reserved 1 USERSETMPEND Enables unprivileged software access to the STIR see Software Trigger Interrupt Register ...

Page 144: ...ignments Bits Name Function 31 24 PRI_7 Reserved 23 16 PRI_6 Priority of system handler 6 UsageFault 15 8 PRI_5 Priority of system handler 5 BusFault 7 0 PRI_4 Priority of system handler 4 MemManage Table 61 SHPR2 Bit Assignments Bits Name Function 31 24 PRI_11 Priority of system handler 11 SVCall 23 0 Reserved Table 62 SHPR3 Bit Assignments Bits Name Function 31 24 PRI_15 Priority of system handl...

Page 145: ...g bit reads as 1 if exception is pendingb 13 MEMFAULTPENDED MemManage fault exception pending bit reads as 1 if exception is pendingb 12 USGFAULTPENDED UsageFault exception pending bit reads as 1 if exception is pendingb 11 SYSTICKACT SysTick exception active bit reads as 1 if exception is active3 10 PENDSVACT PendSV exception active bit reads as 1 if exception is active 9 Reserved 8 MONITORACT De...

Page 146: ...0 page 102 for its attributes The bit assignments are Figure 41 CFSR Bit Assignments The following subsections describe the sub registers that make up the CFSR The CFSR is byte accessible You can access the CFSR or its sub registers as follows access the complete CFSR with a word access to 0xE000ED28 access the MMFSR with a byte access to 0xE000ED28 access the MMFSR and BFSR with a halfword access...

Page 147: ...ns When this bit is 1 the SP is still adjusted but the values in the context area on the stack might be incorrect The processor has not written a fault address to the MMAR 3 MUNSTKERR MemManage fault on unstacking for a return from exception 0 no unstacking fault 1 unstack for an exception return has caused one or more access violations This fault is chained to the handler This means that when thi...

Page 148: ...a MemManage fault occurring later If a BusFault occurs and is escalated to a HardFault because of priority the HardFault handler must set this bit to 0 This prevents problems if returning to a stacked active BusFault handler whose BFAR value has been overwritten 6 5 Reserved 4 STKERR BusFault on stacking for exception entry 0 no stacking fault 1 stacking for an exception entry has caused one or mo...

Page 149: ...ata bus error has occurred and the PC value stacked for the exception return points to the instruction that caused the fault When the processor sets this bit is 1 it writes the faulting address to the BFAR 0 IBUSERR Instruction bus error 0 no instruction bus error 1 instruction bus error The processor detects the instruction bus error on prefetching an instruction but it sets the IBUSERR flag to 1...

Page 150: ... no UsageFault caused by attempting to access a coprocessor 1 the processor has attempted to access a coprocessor 2 INVPC Invalid PC load UsageFault caused by an invalid PC load by EXC_RETURN 0 no invalid PC load UsageFault 1 the processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value When this bit is set to 1 the PC value st...

Page 151: ...ested by the instruction even if it is not the address of the fault Table 67 HFSR Bit Assignments Bits Name Function 31 DEBUGEVT Reserved for Debug use When writing to the register you must write 0 to this bit otherwise behavior is Unpredictable 30 FORCED Indicates a forced HardFault generated by escalation of a fault with configurable priority that cannot be handles either because of priority or ...

Page 152: ...o system control block registers In a fault handler to determine the true faulting address Read and save the MMFAR or BFAR value Read the MMARVALID bit in the MMFSR or the BFARVALID bit in the BFSR The MMFAR or BFAR address is valid only if this bit is 1 Software must follow this sequence because another higher priority exception might change the MMFAR or BFAR value For example if a higher priorit...

Page 153: ...summary in Table 71 page 119 for its attributes The bit assignments are Figure 47 SYST_RVR Register Bit Assignments 1 SysTick calibration value Table 72 SYST_CTRL Register Bit Assignments Bits Name Function 31 17 Reserved 16 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read 15 3 Reserved 2 CLKSOURCE Selects the SysTick timer clock source 1 processor clock Determined by STCLK_...

Page 154: ...on Value Register The SYST_CALIB register indicates the SysTick calibration properties See the register summary in Table 71 page 119 for its attributes The bit assignments are Figure 49 SYST_CALIB Register Bit Assignments 23 0 RELOAD Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0 see Calculating the RELOAD Value page 121 Table 74 SYST_CVR Register Bit As...

Page 155: ...havior of memory accesses to the region The Cortex M3 processor MPU defines eight separate memory regions 0 7 a background region When memory regions overlap a memory access is affected by the attributes of the region with the highest number For example the attributes for region 7 take precedence over the attributes of any region that overlaps region 7 The background region has the same memory acc...

Page 156: ...l memory that only a single processor uses Table 77 MPU Registers Summary Address Name Type Required privilege Reset value See 0xE000ED90 MPU_TYPE RO Privileged 0x00000800 MPU Type Register page 124 0xE000ED94 MPU_CTRL RW Privileged 0x00000000 MPU Control Register page 124 0xE000ED98 MPU_RNR RW Privileged 0x00000000 MPU Region Number Register page 125 0xE000ED9C MPU_RBAR RW Privileged 0x00000000 M...

Page 157: ...calated handlers See the register summary in Table 77 page 123 for the MPU_CTRL attributes The bit assignments are Figure 51 MPU_CTRL Register Bit Assignments continued Table 78 MPU_TYPE Register Bit Assignments Bits Name Function 31 24 Reserved 23 16 IREGION Indicates the number of supported MPU instruction regions Always contains 0x00 The MPU memory map is unified and is described by the DREGION...

Page 158: ...handler for an exception with priority 1 or 2 These priorities are only possible when handling a HardFault or NMI exception or when FAULTMASK is enabled Setting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities 3 7 4 3 MPU Region Number Register The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers See the register summary in Tabl...

Page 159: ...efines the value of N N Log2 Region size in bytes Table 80 MPU_RNR Bit Assignments Bits Name Function 31 8 Reserved 7 0 REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers The MPU supports 8 memory regions so the permitted values of this field are 0 7 Table 81 MPU_RBAR Bit Assignments Bits Name Function 31 N ADDR Region base address field The value of N depends on the...

Page 160: ...bits The bit assignments are Figure 54 MPU_RASR Bit Assignments For information about access permission refer to MPU Access Permission Attributes page 128 Table 82 MPU_RASR Bit Assignments Bits Name Function 31 29 Reserved 28 XN Instruction access disable bit 0 instruction fetches enabled 1 instruction fetches disabled 27 Reserved 26 24 AP Access permission field see Table 86 page 129 23 22 Reserv...

Page 161: ...ues SIZE value Region size Value of N1 1 In the MPU_RBAR see MPU Region Base Address Register page 126 Note b00100 4 32B 5 Minimum permitted size b01001 9 1KB 10 b10011 19 1MB 20 b11101 29 1GB 30 b11111 31 4GB 32 Maximum possible size Table 84 TEX C B and S Encoding TEX C B S Memory type Shareability Other attributes b000 0 0 x1 1 The MPU ignores the value of this bit Strongly ordered Shareable 1 ...

Page 162: ...ogram up to four regions simultaneously using an STM instruction Updating an MPU region using separate words Simple code to configure one region R1 region number R2 size enable R3 attributes R4 address LDR R0 MPU_RNR 0xE000ED98 MPU region number register STR R1 R0 0x0 Region Number STR R4 R0 0x4 Region Base Address Table 85 Cache Policy for Memory Attribute Encoding Encoding AA or BB Corresponding...

Page 163: ...avior Software does not need any memory barrier instructions during MPU setup because it accesses the MPU through the PPB which is a Strongly Ordered memory region For example if you want all of the memory access behavior to take effect immediately after the programming sequence use a DSB instruction and an ISB instruction A DSB is required after changing MPU settings such as at the end of context...

Page 164: ...sizes you must set the SRD field to 0x00 otherwise the MPU behavior is Unpredictable Example of SRD use Two regions with the same base address overlap Region one is 128KB and region two is 512KB To ensure the attributes from region one apply to the first128KB region set the SRD field for region two to b00000011 to disable the first two subregions as shown in the following figure Figure 55 SRD Fiel...

Page 165: ...the application code more portable The values given are for typical situations In special systems such as multiprocessor designs or designs with a separate DMA engine the shareability attribute might be important In these cases refer to the recommendations of the memory device manufacturer Table 87 Memory Region Attributes for a Microcontroller Memory region TEX C B S Memory type and attributes Fl...

Page 166: ...Cortex M3 Processor Reference Material UG0331 User Guide Revision 15 0 132 ...

Page 167: ...cessor can write to Cache Memory through the System bus SBUS Zero wait state in case of a hit instruction in Cache Memory and can run up to the maximum system frequency Supports Cache locked mode Cache is constructed of latches The following figure depicts the connectivity of the Cache Controller in a SmartFusion2 device Figure 56 Cache Controller Interfaces to Cortex M3 Processor AHB Bus Matrix a...

Page 168: ...e same time another master accesses another slave If more than one master attempts to access the same slave simultaneously arbitration is performed Each of the slave devices contains an arbiter which manages accesses when more than one master attempts to access a slave at the same time 4 2 2 Memory Mapping The following sections explain memory mapping for eNVM eSRAM and DDR address spaces to cache...

Page 169: ...ble using eSRAM Remapped mode Table 88 Default eNVM Remapped Mode Data Code Region Space Address CM3 Data Region Reserved 0xE000_0000 to 0xFFFF_FFFF DDR _SPACE 3 256 MB 0xD000_0000 to 0xDFFF_FFFF DDR _SPACE 2 256 MB 0xC000_0000 to 0xCFFF_FFFF DDR_ SPACE 1 256 MB 0xB000_0000 to 0xBFFF_FFFF DDR _SPACE 0 256 MB 0xA000_0000 to 0xAFFF_FFFF eNVM Remap Area etc 1 GB 0x6000_0000 to 0x9FFF_FFFF Peripheral ...

Page 170: ...h are first checked in the Cache Engine that is MS4 and from there to Cache Memory If not present then as shown in the following table the corresponding routing slave will be selected For eNVM Remap mode it is switch MS2 The following are the abbreviations used in the table IC Instruction CODE ICODE Cacheable INC ICODE Non Cacheable NC Non Cacheable DC Data CODE DCODE Cacheable CM3 Code Region DDR...

Page 171: ...DR MS5 MSS DDR Bridge NC NON DDR MS1 AHB Bus Matrix 2 eSRAM Remapped ICODE INC eNVM MS2 AHB Bus Matrix INC DDR MS3 MSS DDR Bridge INC eSRAM MS2 AHB Bus Matrix DCODE DNC eNVM MS0 AHB Bus Matrix DNC R DDR MS3 MSS DDR Bridge DNC W DDR MS5 MSS DDR Bridge DNC eSRAM MS0 AHB Bus Matrix SBUS NC DDR MS5 MSS DDR Bridge NC NON DDR MS1 AHB Bus Matrix GBUS NC DDR MS5 MSS DDR Bridge NC NON DDR MS1 AHB Bus Matri...

Page 172: ...mpts a read access from an unimplemented address space the cache matrix completes the handshake with the master with HRESP error indication Garbage data is returned in this case The cache matrix supports locked transactions from the SBUS towards the eSRAM AHB controller through the switch by monitoring HMASTLOCK The cache matrix initiates IDLE on the AHB bus after every LOCKED transfer SmartFusion...

Page 173: ...f the memory contains 64 bit information the required data can be selected by using the second bit from the memory address as shown in the figure Figure 58 General Cache Architecture and Addressing The Cache Engine has two buses interacting with the ICode and DCode buses through interfaces MS3 and MS4 It supports the following functionalities 1 Only read transfers from ICode and DCode bus are cach...

Page 174: ...es do not exhibit this behavior when using Libero 11 4 SP1 or later IAR tool chain users can do a work around for this problem by preventing the Cortex M3 processor from issuing concurrent I and D buses access through the cache To implement this work around updates are required to the IAR tool chains All libraries must be fully rebuilt from the source code to avoid this interaction by preventing t...

Page 175: ... directly read from the cache and the cache is not invalidated or refilled for normal operations The memory region beyond 8 KB is treated as non cacheable and accessed as per the prevailing memory map In Cache Locked mode if an uncorrectable error is detected for cacheable address 0 to 8 KB then the cache line is fetched from the main memory using the cache lock base address and the entire cache l...

Page 176: ...ata reads and 32 bit AHB Lite to access DDR memory through DDR bridge and system bus read and write access 2 Interface towards AHB bus matrix There are three 32 bit AHB Lite modes Read write for non cacheable data access to eSRAM eNVM Read write from SBus Read write from ICode bus Figure 61 Cache Controller Interface Cortex M3 Processor Cache Controller MSS DDR Bridge MDDR Subsystem AHB Bus Matrix...

Page 177: ... design software The following figure shows the Cache Controller enable option cache region size selection Figure 62 MSS Configurator with Cache Controller Configuration Options The following figure shows how to select the main memory from memory blocks eNVM eSRAM and DDR SDRAM Figure 63 MSS Configurator with Remapping Options for eNVM eSRAM and MDDR ...

Page 178: ...te data sections are in non cacheable memory regions or accessed through the system bus address space This note has to be strictly followed if eSRAM or DDR SDRAM are selected as the main memory for the cache 4 3 1 System Registers Used for Cache Operations Detailed bit level descriptions of the cache registers are provided in the System Register Block page 670 Table 92 System Registers for Cache O...

Page 179: ... 256 KB each The total eNVM size is 512 KB In devices with two blocks present any two masters can accesses the eNVM blocks eNVM_0 and eNVM_1 in parallel which improves the overall performance of the system As shown in the following figure the eNVM block s is connected as slave to the AHB bus matrix Figure 65 eNVM Connection to AHB Bus Matrix AHB Bus Matrix eSRAM_0 System Controller Cache Controlle...

Page 180: ...6 eNVM Controller Block Diagram M3_CLK is used within the MSS to clock the AHB bus matrix Refer to UG0449 SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information on M3_CLK Table 93 eNVM Address Locations Device eNVM_0 eNVM_1 Total NVM M2S005 0x60000000 None 128 KB M2S010 0x60000000 None 256 KB M2S025 0x60000000 None 256 KB M2S050 0x60000000 None 256 KB M2S060 0x60000000 None 256...

Page 181: ...y To support an 8 bit fixed length wrapping burst four eNVM read cycles are automatically invoked and data read from the eNVM is stored in RDBUFF Read data is presented to HRDATA when the data for the current read address becomes available Assembly Buffer AB The eNVM is page based flash memory Only one page of data 1 024 bits can be written at a time The assembly buffer stores thirty two 32 bit da...

Page 182: ... from the write data buffer WDBUFF Data can be written to WDBUFF in byte half word or word AHB transfers Data for Page Program comes from WDBUFF or user data previously written into AB Command code in Table 98 page 151 determines the NVM commands to be issued The eNVM user data array is treated as ROM so any program operations must be performed by submitting relevant commands to the controller Any...

Page 183: ...urned immediately on the AHB bus otherwise a 64 bit read access of the eNVM is initiated and will take several clock cycles as configured by ENVM_CR register The eNVM data is stored in the read data buffer and provided to the AHB bus Assuming that the eNVM address is incremented the data value stored in the read data buffer is available for the next AHB read cycle 6HFWRU 6HFWRU Q 6HFWRU Q H190 WR ...

Page 184: ...s 16 double words 32 words requires an AHBL address map as specified in the following table When programming the eNVM sector and page addresses must be programmed into the command CMD register as specified in Table 98 page 151 5 2 4 3 eNVM Commands The eNVM commands are explained in the Table 98 page 151 The eNVM Command register is used to program the eNVM commands The following section explains ...

Page 185: ...til the firmware recovers When the AHBL triggers a write transaction with HADDR 18 0 0 148 HWDATA is treated as a command CMD CMD 31 24 will be decoded as the eNVM operation as mentioned in Figure 68 page 150 The value from CMD 23 3 will be decoded as the NVM array address for the eNVM operation Depending on the command code some LSB bits of CMD 23 0 will be ignored For example to submit a program...

Page 186: ...age address to be programmed ProgramDa Once the ProgramAd command is issued data can be written to AB ProgramStart After ProgramAd and ProgramDa optional ProgramStart can be used to start the NVM operation Once the NVM operation starts and until it finishes any further NVM accessing AHBL transaction will result in HREADYOUT going Low until the operation is done ProgramADS 1 ACMD 08 PGA Write Start...

Page 187: ...ata can be written to AB VerifyStart After VerifyAd and VerifyDa optional VerifyStart can be used to start the NVM operation Once the NVM operation starts and until it finishes any further NVM accessing AHBL transaction will result in HREADYOUT going Low until the operation is done If the VerifyDa command is not issued after the VerifyAd operation the current data in assembly buffer is verified wi...

Page 188: ...e 69 Timing Diagram Showing Single Word Read Operation 5 2 5 5 2 Consecutive Reads Incrementing through Memory In this case four reads from addresses 0x60000010 0x60000014 0x60000018 and 0x6000001C are initiated by the AHB master in succession The first word is returned 9 clock cycles later as shown in the preceding figure but the second word occurs in the following cycle 9 clock cycles later the ...

Page 189: ...rocessor operating at 166 MHz The eNVM NV_FREQRNG is set to 15 The sample eNVM operation programs the eNVM sector 0 page 4 with random data and verifies the eNVM sector 0 page 4 Note In all the waveforms the eNVM controller register offset is shown in AHB address line HADDR Refer to eNVM Control Registers page 180 for more information 5 2 5 6 1 Sequence of eNVM Program and Verify Operations when u...

Page 190: ...wn in waveforms See Figure 73 page 156 through Figure 76 page 157 The Cortex M3 processor gets the exclusive register access by writing 0x1 to the REQACCESS register It reads the value 0x5 from AHB read data line HRDATA it means the exclusive register access is issued Then the WDBUFF Write Data Buffer register is filled with the random data as shown in the following figure Figure 73 Exclusive Regi...

Page 191: ... register access by writing 0x1 to the REQACCESS register Refer to Figure 78 page 158 2 Fills the WDBUFF Write Data Buffer register with the data to be written to the eNVM array Refer to Figure 78 page 158 3 Issues ProgramAD command Refer to Figure 79 page 158 4 Completes the ProgramAD command and Issues the ProgramDA command Refer to Figure 80 page 158 5 Completes the ProgramDA command and Issues...

Page 192: ...erify operation is completed Refer to the preceding figure The eNVM commands sequence is explained in waveforms in Figure 78 page 158 through Figure 81 page 159 The following figure shows the Cortex M3 master requesting for exclusive register access and filling WDBUFF Write Data Buffer Figure 78 Exclusive Register Access and Filling Data in WDBUFF The following figure shows the issuance of the Pro...

Page 193: ...h as the assertion of any status bit from eNVM or when an internal eNVM operation ends After HINT is asserted the Cortex M3 processor determines the next steps The Cortex M3 processor can respond to the interrupt and then clear HINT by writing 1 to bit 0 of the write only register CLRHINT 2 0 HADDR 0x158 in Table 112 page 180 If the Cortex M3 processor decides to ignore the interrupt by masking it...

Page 194: ...an be protected from the FPGA fabric 5 3 1 User Protectable 4K Regions Figure 82 eNVM Special Sectors for the M2S050TS Device with 256 KB eNVM_0 Figure 83 eNVM Special Sectors for the M2S005S Device with 128 KB eNVM_0 WR WR H190B 7RWDO 6SHFLDO 6HFWRU 8SSHU 5HJLRQ 8 6SHFLDO 6HFWRU RZHU 5HJLRQ 0 6 76 WR WR H190B 7RWDO 6SHFLDO 6HFWRU 8SSHU 5HJLRQ 8 6SHFLDO 6HFWRU RZHU 5HJLRQ 0 6 6 WR WR 6SHFLDO 6HFWR...

Page 195: ...M_0 Figure 85 eNVM Special Sectors for the M2S060TS Devices with 256 KB eNVM_0 WR WR H190B 7RWDO 6SHFLDO 6HFWRU 8SSHU 5HJLRQ 8 6SHFLDO 6HFWRU RZHU 5HJLRQ 0 6 76 0 6 76 WR WR 6SHFLDO 6HFWRU RZHU 5HJLRQ 6SHFLDO 6HFWRU 8SSHU 5HJLRQ 8 WR WR H190B 7RWDO 3ULYDWH 5HJLRQ 6SHFLDO 6HFWRU RZHU 5HJLRQ 0 6 76 WR WR 3ULYDWH 5HJLRQ 6SHFLDO 6HFWRU 8SSHU 5HJLRQ 8 ...

Page 196: ...rs 5 3 1 2 Write Protection When AHB masters other than system controller issue write transactions which may be one of the program commands supported by this interface to protected regions the address and protection configuration is checked to determine whether the transaction is targeted to the protected region If the transaction is not allowed no command is sent to eNVM and the Status bit is ass...

Page 197: ... sector N 1 of the last eNVM module are used for special purpose storage like device certificate and eNVM digest Some special purpose pages are reserved and protected Refer below tables for more information on eNVM special purpose storage based on SmartFusion2 device density The system controller performs read write operations on unreserved eNVM pages using system controller services It only reads...

Page 198: ...30 Unreserved User Defined Key sizes Exported bit Valid bit byte array 56 bytes holds 56 key sizes along with exported and valid bit flags 40 55 0 30 Unreserved Reserved for future use 96 31 0 31 Unreserved User PK X 384 bit User PUF ECC Public Key 0 47 0 31 Unreserved User PK Y 384 bit User PUF ECC Public Key 48 47 0 31 Unreserved User Activation Code exported flag Digests Valid Activation Code m...

Page 199: ...ows the initial System Builder window where the required device features can be selected For details on how to launch the System Builder wizard and detailed information on how to use it refer to SmartFusion2 System Builder User Guide N 1 0 Unreserved User Key Code 0 256 bit User AES Key 0 43 0 0 Unreserved User Key Code 1 384 bit User PUF ECC Key 76 bytes 44 75 0 0 Unreserved Reserved for future u...

Page 200: ...Embedded NVM eNVM Controllers UG0331 User Guide Revision 15 0 166 Figure 87 System Builder Window ...

Page 201: ...a programming file with the eNVM client in an application using System Builder 1 Check the MSS On chip Flash Memory eNVM check box under the Device Features tab and leave the other check boxes unchecked The following figure shows the System Builder Device Features tab Figure 88 System Builder Device Features Tab ...

Page 202: ...ck Add to System The following figure shows the Add Data Storage Client dialog It supports the following file for mats Intel Hex Motorola S Microsemi Hex Microsemi Binary 4 Create the memory file in any one of the above formats with the executable code or data Memory file can be created for the code using the SoftConsole 3 4 or later with the linker script production execute in place ld For more d...

Page 203: ... navigate to the memory file location using Browse and select it Give the rest of the parameters according to the requirements and click OK to add the eNVM client For more information on Use absolute addressing Use as ROM and other options click Help Figure 90 Add Data Storage Client Dialog ...

Page 204: ...ser Guide Revision 15 0 170 6 The eNVM client data is populated in the System Builder Memories tab The following figure shows the System Builder Memories tab with two eNVM clients Figure 91 System Builder Memories Tab with Two eNVM Clients ...

Page 205: ... to AC390 SmartFusion2 SoC FPGA Remapping eNVM eSRAM and DDR SDR SDRAM Memories Application Note Figure 92 System Builder Microcontroller Tab Notes The code executing from eNVM can program the other regions of eNVM memory Ensure that the code executing region must not be overwritten If the user design is using the FPGA fabric based master the Cortex M3 processor requires a valid program in eNVM fr...

Page 206: ...ng Generate Component 11 Double click Run PROGRAM Action in the Libero Design Flow window to program the SmartFusion2 device to initialize the eNVM with the memory file Notes The MSS eNVM supports full behavioral simulation models Refer to SmartFusion2 MSS Embedded Nonvolatile Memory eNVM Simulation User Guide for information on how to simulate the eNVM operations Refer to the AC429 SmartFusion2 a...

Page 207: ...ect Microsemi provides eNVM firmware drivers to use with the application development The SmartFusion2 eNVM firmware drivers can be downloaded from the Firmware Catalog The eNVM firmware driver provides APIs to unlock and write to eNVM features Refer to the SmartFusion2 eNVM Driver User Guide from Open Documentation for the list of APIs and their descriptions The eNVM driver package includes sample...

Page 208: ...ut data This function is a blocking function The NVM_write function performs a verify operation on each page programmed to ensure the NVM is programmed with the expected content Table 103 SYSREG Control Registers Register Name Register Type Flash Write Protect Reset Source Description ENVM_CR 0x4003800C RW P Register sysreset_n eNVM Configuration register ENVM_REMAP_BASE_CR 0x40038010 RW P Registe...

Page 209: ... off after every read cycle if an idle cycle follows This saves power but slightly increases access time on the next read cycle 1 The sense amp is turned ON This increases power but decreases access times 15 ENVM_PERSIST 0 Reset control for NVM0 and NVM1 0 NVM0 NVM1 will get reset on SYSRESET_N and PORESET_N 1 NVM0 NVM1 will get reset on PORESET_N 14 NV_DPD1 0 Deep power down control for the NVM1 ...

Page 210: ...er modes Page program and Page verify 3 0110 Page Read 7 All other modes Page program and Page verify 3 0111 Page Read 8 All other modes Page program and Page verify 4 1000 Page Read 9 All other modes Page program and Page verify 4 1001 Page Read 10 All other modes Page program and Page verify 4 1010 Page Read 11 All other modes Page program and Page verify 5 1011 Page Read 12 All other modes Page...

Page 211: ... KB 1 0 0 1 0 512 KB reset value Table 106 ENVM_REMAP_BASE_CR Bit Number Name Reset Value Description 31 19 Reserved 0 Reserved 18 1 SW_ENVMREMAPBASE 0 Offset address of eNVM for remapping SW_ENVMREMAPBASE indicates the offset within eNVM address space of the base address of the segment in eNVM which is to be remapped to location 0x00000000 Bit 0 of this register is defined as SW_ENVMREMAPENABLE a...

Page 212: ...ption 31 16 Reserved 0 15 NVM1_UPPER_WRITE_ALLOWED 0x1 When set indicates that the masters who have read access can have write access to the upper protection region of eNVM1 This is updated by the user flash row bit 14 NVM1_UPPER_OTHERS_ACCESS 0x1 When set indicates that the other masters can access the upper protection region of eNVM1 This is set by the user flash row bit 13 NVM1_UPPER_FABRIC_ACC...

Page 213: ... of eNVM0 This will be set by the user flash row bit 3 NVM0_LOWER_WRITE_ALLOWED 0x1 When set indicates that the masters who have read access can have write access to the lower protection region of eNVM0 This will be set by the user flash row bit 2 NVM0_LOWER_OTHERS_ACCESS 0x1 When set indicates that the other masters can access the lower protection region of eNVM0 This will be set by the user flas...

Page 214: ...and eNVM_1 Table 110 ENVM_SR Bit Number Name Reset Value Description 31 2 Reserved 0 1 0 ENVM_BUSY 0 Active high signals indicate a busy state per eNVM for CLK driven operations and for internal operations triggered by the write program erase transfer command ENVM_BUSY 1 Busy indication from ENVM1 ENVM_BUSY 0 Busy indication from ENVM0 Table 111 eNVM Control Registers Base Address eNVM Block Contr...

Page 215: ...NV_FREQRNG 3 0 is for NVM0 wait states and NV_FREQRNG 7 4 is for NVM1 wait states Refer to Table 114 on page 185 NV_FREQRNG calculations at different M3_CLK frequencies for all SmartFusion2 devices Bits 7 4 are unused with the AHB NVM block when the device has only eNVM_0 This controls the NV_FREQRNG 3 0 input on the NVMCTRL function that sets the required number of clock cycles required for NVM a...

Page 216: ...aster Write size in number of double words to be written to assembly buffer from Write Data buffer during NVM commands See description for individual commands 0000 1 dword 1111 16 dwords 0x148 CMD 31 0 R W 0 Exclusive access to the requested master Write to CMD and if command field in HWDATA decoded to be a command then NVM command will be initiated See description of Table 103 page 174 CMD regist...

Page 217: ...tten with 0x01 it will request exclusive access Read indicates whether access has granted or not or which entity currently has been granted access Read Value 2 0 0XX No entity has access The XX value indicates who had last access 100 System controller 101 M3 110 Fabric 111 Other master such as PDMA or HDMA To release access rights write 0x00 The System Controller may gain immediate access by writi...

Page 218: ...error 1 bit corrected 00 no error 01 1 bit corrected 10 2 bit detected 11 3 or more bits detected 12 11 RDBUFF1 Read data buffer 1 Read data buffer 127 64 ECC status 2 bit error 1 bit corrected 00 no error 01 1 bit corrected 10 2 bit detected 11 3 or more bits detected 10 9 RDBUFF0 Read data buffer 0 Read data buffer 63 0 ECC status 2 bit error 1 bit corrected 00 no error 01 1 bit corrected 10 2 b...

Page 219: ...FREQRNG 7 0 0x77 0x66 0x55 0x44 0x33 0x22 0x22 Table 115 NV_PAGE_STATUS Bit Description 1 R W page status select 0 Reserved Table 116 INTEN 10 0 Bit Description 10 Command loaded when busy 9 NVM command denied by protection 8 NVM internal operation erase program write only is complete 7 ECC2 2 bit error 6 ECC1 1 bit correction 5 Refresh required 4 Write count is over threshold 3 Program or erase f...

Page 220: ...ded NVM eNVM Controllers UG0331 User Guide Revision 15 0 186 Table 117 CLRHINT 2 0 Bit Description 2 Clear the internal command when busy bit 1 Clear the internal access denied flag 0 Clear HINTERRUPT output ...

Page 221: ...aving two blocks eSRAM_0 and eSRAM_1 maximizes hardware parallelism For example at the same instant that the Cortex M3 processor is reading from eSRAM_0 the Ethernet controller can read from eSRAM_1 independently The eSRAM address space is byte half word 16 bit and word 32 bit addressable A pipeline is provided to address the latency issues at higher speeds of operation As shown in the following f...

Page 222: ...0011FFF 16 KB from 0x20004000 to 0x20007FFF and 4 KB from 0x20011000 to 0x20011FFF eSRAM_1 RAM4096X40_2 16 KB from 0x20008000 to 0x2000BFFF and ECC from 0x20012000 to 0x20012FFF 16 KB from 0x20008000 to 0x2000BFFF and 4 KB from 0x20012000 to 0x20012FFF RAM4096X40_3 16 KB from 0x2000C000 to 0x2000FFFF and ECC from 0x20013000 to 0x20013FFF 16 KB from 0x2000C000 to 0x2000FFFF and 4 KB from 0x20013000...

Page 223: ...t directly to the memory input If the access is for additional 8 KB memory then the address for a particular byte of HWDATA will be selected based on the shift address Address MUX This utilizes the AHB address bus HADDR and HADDRU an additional HADDR bit for selecting upper 8 K bank of the RAM Based on the FSM internal signals output ADDR is generated and passed to the memory The shifted address i...

Page 224: ...rganized as 4096 40 which is 4096 5 bytes When ECC is enabled the fifth byte stores ECC values for the 32 bits of data When ECC is disabled the fifth byte location is used to create an additional 2 KB of user memory Four locations are used for each 32 bit word The following table shows the organization of 4096 40 bits in SECDED ON mode The total size of the SRAM in the table is 40 KB The locations...

Page 225: ...ror When a 2 bit error is detected during the read part of a read modify write byte or half word operation HRESP is asserted High 6 2 2 2 SECDED OFF SECDED mode can be turned OFF by configuring the EDAC_CR register The total available memory for each eSRAM is 40 KB 1 bit correction and 2 bit detection on the user data is not applicable in this mode 6 2 3 Pipeline Modes and Wait States for Read and...

Page 226: ...ode and Pipeline mode In Pipeline mode the FIC interface adds one extra clock cycle for read and write so the overall latency for accessing the eSRAM increases in this case Table 121 Wait States in Different Operation Modes Pipeline eSRAM SECDED Mode Operation Size Number of Wait States Number of Wait States Reads following a Write Enabled 32 KB RAM SECDED ON Mode Write 32 Bit 0 1 16 Bit 1 3 8 Bit...

Page 227: ... Bit 0 1 SECDED OFF Mode Write 32 Bit 0 0 16 Bit 0 0 8 Bit 0 0 Read 32 Bit 0 1 16 Bit 0 1 8 Bit 0 1 8 KB RAM SECDED OFF Mode Write 32 Bit 1 1 16 Bit 0 0 8 Bit 0 0 Read 32 Bit 1 2 16 Bit 0 1 8 Bit 0 1 Table 121 Wait States in Different Operation Modes continued Pipeline eSRAM SECDED Mode Operation Size Number of Wait States Number of Wait States Reads following a Write ...

Page 228: ...The following figure shows the initial System Builder window where the required device features can be selected For details on how to launch the System Builder wizard and a detailed information on how to use it refer to the SmartFusion2 System Builder User Guide Figure 97 System Builder Window Any master for example Cortex M3 processor FPGA fabric master HPDMA or PDMA connected to the AHB bus matr...

Page 229: ...uilder window to configure Programmable Slave Maximum Latency for eSRAM_0 and eSRAM_1 blocks The following figure shows the System Builder Microcontroller tab For more information on the Programmable Slave Maximum Latency configuration and remapping eSRAM to Cortex M3 code space click Help and select AHB Bus Matrix document as shown in the figure Refer to AC390 SmartFusion2 SoC FPGA Remapping eNVM...

Page 230: ...em Builder SECDED tab For more information on SECDED click Help and select SECDED document Refer to UG0388 SmartFusion2 SoC FPGA Error Detection and Correction of eSRAM Memory Demo User Guide Figure 99 System Builder SECDED Tab The SECDED feature can be enabled or disabled by selecting Enable EDAC for eSRAM_0 and eSRAM_1 The interrupts for 1 bit error or 2 bit error or both 1 bit and 2 bit errors ...

Page 231: ...sion2 MSS Security Configuration Figure 100 System Builder Security Tab 4 Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs and click Finish to proceed with creating the MSS Subsystem 5 Do required Pin connections and Save the project Generate the SmartDesign in Libero by clicking Generate Component 6 Double click Run PROGRAM Action in the Libero Design...

Page 232: ...M memory ESRAM0_EDAC_CNT 0x400380F0 RO N A SYSRESET_N Represents 1 bit error count of eSRAM_0 ESRAM1_EDAC_CNT 0x400380F4 RO N A SYSRESET_N Represents 1 bit error count of eSRAM_1 ESRAM0_EDAC_ADR 0x4003810C RO N A SYSRESET_N Address from eSRAM_0 on which 1 bit ECC error has occurred ESRAM1_EDAC_ADR 0x40038110 RO N A SYSRESET_N Address from eSRAM_1 on which 1 bit ECC error has occurred MM0_1_2_SECUR...

Page 233: ...RESET_N Enable disable of 1 bit error 2 bit error status update for eSRAM_0 and eSRAM_1 This can be set by the System Builder also using settings on the SECDED tab EDAC_CR 0x40038038 RW P Register SYSRESET_N EDAC enable disable and soft reset for eSRAM_0 and eSRAM_1 This can be set by the System Builder also using settings on the SECDED tab Table 123 ESRAM_CR Bit Number Name Reset Value Descriptio...

Page 234: ... that eNVM or MDDR is present at location 0x00000000 1 eSRAM_0 and eSRAM_1 are remapped to location 0x00000000 of Cortex M3 processor ICODE DCODE space Table 124 ESRAM_MAX_LAT Bit Number Name Reset Value Description 31 6 Reserved 0 Reserved 5 3 SW_MAX_LAT_ESRAM1 0x1 Defines the maximum number of cycles the processor bus will wait for eSRAM1 when it is being accessed by a master with a weighted rou...

Page 235: ...s maximum value 15 0 ESRAM0_EDAC_CNT_1E 0 16 bit counter that counts the number of 1 bit corrected errors for eSRAM0 The counter will not roll back and will stay at its maximum value Table 128 ESRAM1_EDAC_CNT Bit Number Name Reset Value Description 31 16 ESRAM1_EDAC_CNT_2E 0 16 bit counter that counts the number of 2 bit uncorrected errors for eSRAM1 The counter will not roll back and will stay at...

Page 236: ...ave 3 eNVM1 If not set Masters 0 1 and 2 will not have write access to Slave 3 6 MM0_1_2_MS3_ALLOWED_R 1 Read security bits for Masters 0 1 and 2 to Slave 3 eNVM1 If not set Masters 0 1 and 2 will not have read access to Slave 3 5 MM0_1_2_MS2_ALLOWED_W 1 Write security bits for Masters 0 1 and 2 to Slave 2 eNVM0 If not set Masters 0 1 and 2 will not have write access to Slave 2 4 MM0_1_2_MS2_ALLOW...

Page 237: ... eNVM1 If not set masters 4 5 and DDR_FIC will not have read access to slave 3 5 MM4_5_DDR_FIC_MS2_ALLOWED_W 1 Write Security Bits for masters 4 5 and DDR_FIC to slave 2 eNVM0 If not set masters 4 5 and DDR_FIC will not have write access to slave 2 4 MM4_5_DDR_FIC_MS2_ALLOWED_R 1 Read security bits for masters 4 5 and DDR_FIC to slave 2 eNVM0 If not set masters 4 5 and DDR_FIC will not have read a...

Page 238: ...ers 3 6 7 and 8 will not have write access to slave 2 4 MM3_6_7_8_MS2_ALLOWED_R 1 Read security bits for masters 3 6 7 and 8 to slave 2 eNVM0 If not set masters 3 6 7 and 8 will not have read access to slave 2 3 MM3_6_7_8_MS1_ALLOWED_W 1 Write security bits for masters 3 6 7 and 8 to slave 1 eSRAM1 If not set masters 3 6 7 and 8 will not have write access to slave 1 2 MM3_6_7_8_MS1_ALLOWED_R 1 Rea...

Page 239: ... set master 9 will not have write access to slave 0 0 MM9_MS0_ALLOWED_R 1 Read security bits for master 9 to slave 0 eSRAM0 If not set master 9 will not have read access to slave 0 Table 135 EDAC_SR Bit Number Name Reset Value Description 31 14 Reserved 0 Reserved 13 CAN_EDAC_2E 0 Updated by CAN when a 2 bit SECDED error has been detected for RAM memory 12 CAN_EDAC_1E 0 Updated by CAN when a 1 bit...

Page 240: ... value in USB corresponding to the count value of EDAC 2 bit errors This in turn clears the upper 16 bits of the USB_EDAC_CNT register 10 USB_EDAC_CNTCLR_1E 0 Generated to clear the 16 bit counter value in USB corresponding to the count value of EDAC 1 bit errors This in turn clears the lower 16 bits of the USB_EDAC_CNT register 9 MAC_EDAC_RX_CNTCLR_2E 0 Generated to clear the 16 bit counter value...

Page 241: ... Bit Number Name Reset Value Description 31 15 Reserved 0 Reserved 14 MDDR_ECC_INT_EN 0 Allows the error EDAC for MDDR status update to be disabled Allowed values 0 MDDR_EDAC_2E_EN is disabled 1 MDDR_EDAC_2E_EN is enabled 13 CAN_EDAC_2E_EN 0 Allows the 2 bit error EDAC for CAN status update to be disabled Allowed values 0 CAN_EDAC_2E_EN is disabled 1 CAN_EDAC_2E_EN is enabled 12 CAN_EDAC_1E_EN 0 A...

Page 242: ...enabled 2 ESRAM1_EDAC_1E_EN 0 Allows the 1 bit error EDAC for eSRAM1 status update to be disabled Allowed values 0 ESRAM1_EDAC_1E_EN is disabled 1 ESRAM1_EDAC_1E_EN is enabled 1 ESRAM0_EDAC_2E_EN 0 Allows the 2 bit error EDAC for eSRAM0 status update to be disabled Allowed values 0 ESRAM0_EDAC_2E_EN is disabled 1 ESRAM0_EDAC_2E_EN is enabled 0 ESRAM0_EDAC_1E_EN 0 Allows the 1 bit error EDAC for eS...

Page 243: ...isabled Allowed values 0 Tx RAM EDAC disabled 1 Tx RAM EDAC enabled 2 Reserved 0 Reserved 1 ESRAM1_EDAC_EN 0 Allows the EDAC for eSRAM1 to be disabled Allowed values 0 EDAC disabled 1 EDAC enabled 0 ESRAM0_EDAC_EN 0 Allows the EDAC for eSRAM0 to be disabled Allowed values 0 EDAC disabled 1 EDAC enabled Table 138 EDAC_CR continued ...

Page 244: ...x Nomenclature such as MM0 and MS0 refers to a mirrored master and a mirrored slave A mirrored master port in the matrix connects directly to an AHB master it has the same set of signals but the direction of the signals is described relative to the other end of the connection A mirrored slave port in the matrix connects directly to an AHB slave Only a subset of the full set of theoretical paths is...

Page 245: ...f errors can occur Write by an enabled master to a slave that is not RW Write by an enabled master to addresses not corresponding to a slave Write by the fabric master to the protected region Write by a disabled master to any location Table 139 AHB Bus Matrix Connectivity Masters M3 DCode Bus M3 ICode Bus M3 System Bus System Controller HPDM A FIC_0 FIC_1 MAC PDMA USB MM1 MM0 MM2 MM9 MM3 MM4 MM5 M...

Page 246: ...erconnection To reduce the load on the AHB bus matrix some of the low performance peripherals are connected through the synchronous AHB to AHB bridge with an address decoder The AHB bus matrix is constructed of combinatorial logic except for the AHB to AHB bridge which inserts a one cycle delay in each direction Master Stage 0 Slave Stage 1 Slave Stage 6 Master Stage 9 Master Stage 1 Slave Stage 0...

Page 247: ...ge The MSS APB peripherals are connected through the AHB to APB bus Figure 103 Block Diagram of APB Destinations Connected to AHB Bus Matrix AHB BUS AHB Bus Matrix 10X7 MS5 AHB to AHB bridge with Address decoder MS_APB0 MS_APB1 MS_APB2 AHB to APB_0 AHB to APB_1 AHB to APB_2 MMUART0 MMUART1 SPI_0 SPI_1 I2C_0 I2C_1 DMA CAN WATCHDOG GPIO RTC APB Config bus for MDDR FDDR PCIe etc ...

Page 248: ...or example if Cortex M3 processor master initiates the transactions of read write to the eSRAM slave then the signals with X in the signal name indicates the signals of the Cortex M3 processor and signals with Y indicate slave eSRAM signals Figure 104 AHB Lite Write Transactions HCLK X_HADDR 31 0 X_HTRANS X_HWRITE X_HWDATA 31 0 X_HREADY X_HRESP 0 X_HMASTLOCK 0 Y_HADDR 31 0 Y_HSEL Y_HTRANS Y_HWRITE...

Page 249: ...05 AHB Lite Read Transactions HCLK X_HADDR X_HTRANS X_HWRITE X_HREADY X_HRDATA X_HRESP 0 X_HMASTLOCK 0 Y_HADDR Y_HSEL Y_HTRANS Y_HWRITE Y_HREADY Y_HRDATA Y_HRESP 0 Y_HMASTLOCK 0 AD0 AD1 AD2 AD3 AD4 AD5 D0 D1 D2 D3 D4 D5 AD0 AD1 AD2 AD3 AD4 AD5 D0 D1 D2 D3 D4 D5 ...

Page 250: ... Figure 106 AHB to AHB Write Transactions HCLK Y_HRESET Y_HMASTLOCK Y_HSIZE Y_HSEL Y_HTRANS1 Y_HWRITE Y_HWDATA Y_HADDR Y_HREADY Y_HRESP Y_HREADYOUT X_HREADYOUT X_HRESP X_HADDR X_HSIZE X_HTRANS1 X_HWRITE X_HWDATA X_HREADY X_HMASTLOCK AD0 AD0 D0 D0 11 11 ...

Page 251: ... Figure 107 AHB to AHB Read Transactions HCLK Y_HADDR Y_HMASTLOCK Y_HSIZE Y_HSEL Y_HTRANS1 Y_HWRITE Y_HWDATA Y_HREADY Y_HRESP Y_HRDATA Y_HREADYOUT X_HRDATA X_HREADYOUT X_HRESP X_HADDR X_HSIZE X_HTRANS1 X_HWRITE X_HREADY X_HMASTLOCK AD0 D0 AD0 D0 11 11 ...

Page 252: ...he defined latency period the WRR master will have to re arbitrate for slave access Slave maximum latency can be configurable from one to eight clock cycles eight by default ESRAM_MAX_LAT is only supported for fixed priority masters addressing eSRAM slaves it has no effect on WRR masters The system designer can use this feature to ensure the processor latency for accesses to eSRAM is limited to a ...

Page 253: ...e processor masters have priority over the non processor masters Each non processor master accessing a slave has equal priority on a round robin basis However if a locked transaction occurs the master issuing the lock maintains ownership of the slave until the locked transaction completes Figure 108 Pure Round Robin and Fixed Priority Slave Arbitration Scheme HMASTLOCK Dcode M1 System Controller M...

Page 254: ...de the slave arbitration parameters programmable weight SW_WEIGHT_ master and eSRAM slave maximum latency SW_MAX_LAT_ESRAM 0 1 of ESRAM_MAX_LAT can be configured to operate as WRR arbitration The slave arbiter operates on a round robin basis with each master having a maximum of N consecutive access opportunities to the slave in each round of arbitration The value of N is determined by the programm...

Page 255: ...ng WRR can increase the effective eSRAM bandwidth during this time from 66 to 94 of the theoretical maximum If a sequence of locked transfers is in progress the locked master remains selected by the slave arbiter until the lock sequence is finished regardless of the number of transfers For the case described the values of N and M are SW_WEIGHT_MAC and SW_WEIGHT_HPDMA in the MASTER_WEIGHT0_CR contr...

Page 256: ...ty master has to wait before accessing an eSRAM slave that is currently being accessed by a WRR master When a WRR master has a programmable weight greater than the SW_MAX_LAT_ESRAM 0 1 value the WRR master will have to re arbitrate for the slave after SW_MAX_LAT_ESRAM 0 1 cycles The following equation gives the maximum latency seen by a processor master while accessing an eSRAM slave Maximum laten...

Page 257: ...transfers master issuing lock HMASTLOCK 1 maintains the ownership of the slave as long as lock signal is asserted Figure 110 Slave Arbitration Flow Diagram Slave Arbitration Flow Diagram Re arbitrate Re arbitration Re arbitrate Re arbitrate Re arbitrate Re arbitrate Re arbitrate YES YES YES YES YES YES Transact as long as there is data to transfer Transact till number of transfer PW_MO Transact ti...

Page 258: ...c master FM These interfaces may be configured to operate as AHB32 or APB32 Configure FIC_0 and FIC_1 interfaces in bypass mode to perform weighted round robin arbitration For more information refer to the AC388 SmartFusion2 SoC FPGA Dynamic Configuration of AHB Bus Matrix Application Note FIC_0_MASTER_ID and FIC_1_MASTER_ID are two signals from FIC_0 and FIC_1 to FPGA fabric that indicate the cur...

Page 259: ...0014000 0x21FFFFFF ECC eSRAM_1 ECC eSRAM_1 0x20012000 0x20013FFF ECC eSRAM_0 ECC eSRAM_0 0x20010000 0x20011FFF Cortex M3 processor system region eSRAM_1 eSRAM_1 0x20008000 0x2000FFFF eSRAM_0 eSRAM_0 0x20000000 0x20007FFF 0x00080000 0x1FFFFFFF Cortex M3 processor code region eNVM Cortex M3 processor virtual view eNVM Fabric virtual view 0x0007FFFF Visible only to FPGA fabric master 0x00000000 Memor...

Page 260: ...FFF eNVM_0 eNVM_0 0x60000000 0x6003FFFF FPGA Fabric FIC Region1 FPGA Fabric FIC Region1 0x50000000 0x5FFFFFFF Peripheral bit band alias region of Cortex M3 processor 0x44000000 0x4FFFFFFF Peripherals BB View 0x42000000 0x43FFFFFF 0x40410000 0x41FFFFFF Cache Back door 0x40400000 0x4040FFFF 0x40044000 0x403FFFFF USB USB 0x40043000 0x40043FFF 0x40042000 0x40042FFF Ethernet MAC Control Ethernet MAC Co...

Page 261: ... scheme allows flexibility to the system designer in choosing how much eSRAM is to be dedicated to each class of storage For example if the application stack and heap are small this allows a large chunk of contiguous RAM to be allocated to buffering 7 1 4 1 2 Using Harvard Architecture When a system designer is more interested in optimal performance than flexibility eSRAM_0 can be dedicated to the...

Page 262: ...specific segment of the eNVM array of a specified size to be remapped in the virtual view starting at address 0x00000000 This implies that if multiple firmware images are present each may be built with the assumption that they are located at 0x00000000 For example consider that there are two firmware images image0 and image1 After remap of image1 the virtual view of this image will be from 0x00000...

Page 263: ...7 1 4 4 DDR Remap In default mode the Cortex M3 processor firmware boots from eNVM However as shown in the following figure it is also possible to get the firmware to boot from DDR by re mapping DDR to location zero Code shadowing is supported to facilitate this User boot firmware located in eNVM must copy an executable image from external flash memory serial or parallel to external DDR memory the...

Page 264: ...x40043000 0x40043FFF 0x40042000 0x40042FFF Ethernet MAC Control Ethernet MAC Control 0x40041000 0x40041FFF 0x40039000 0x40040FFF SYSREG SYSREG 0x40038000 0x40038FFF 63 K space allocation for devices outside MSS 0x40030000 0x40037FFF Config DDR_1 PCIe_0 PCIe_1 etc Config DDR_1 PCIe_0 PCIe_1 etc 0x40020400 0x4002FFFF Config DDR_0 Config DDR_0 0x40020000 0x400203FF 0x40018000 0x4001FFFF RTC RTC 0x400...

Page 265: ...s eSRAM DDR FIC_0 and FIC_1 HMASTLOCK signal is not routed to the fabric to allow a matrix to implement a lock based arbitration system 7 1 4 8 Peripheral Bit Banding All of the peripherals including the system registers are located in the peripheral bit banded space of the Cortex M3 processor memory map Therefore bit manipulations may be performed on registers using bit banded instructions from t...

Page 266: ...re the corresponding master port is blocked by a flash configuration bit setting causes the AHB bus matrix to assert HRESP to the master and terminate the transaction If a blocked port is attempting a read access the read data is returned as garbage If the blocked port is attempting a write the write of data does not occur to any slave In both cases one of the SW_ERRORSTATUS bits is asserted DDR_F...

Page 267: ...se the AHB bus matrix in an application 7 2 1 Design Flow The following steps are used to configure the AHB bus matrix in the application 1 Configure the AHB bus matrix by using the MSS configurator in the application as shown in the following figure Figure 118 AHB Bus Matrix in Libero SoC Design MSS Configurator ...

Page 268: ...elect appropriate option from remapping section of AHB Bus Matrix configurator Figure 119 AHB Bus Matrix Configuration Window Enter the weight values for the masters in arbitration section to configure the programmable weight registers MASTER_WEIGHT0_CR and MASTER_WEIGHT1_CR These are located in the SYSREG block with the required weight values The weight values range is from 1 to 32 Enter the maxi...

Page 269: ...nfigures WRR master arbitration scheme for masters MM0_1_2_SECURITY RO U N A SYSRESET_N Security bits for masters 0 1 and 2 MM4_5_DDR_FIC_SECURIT Y MM4_5_FIC64_SECURITY RO U N A SYSRESET_N Security bits for masters 4 5 and DDR_FIC MM3_6_7_8_SECURITY RO U N A SYSRESET_N Security bits for masters 3 6 7 and 8 MM9_SECURITY RO U N A SYSRESET_N Security bits for master 9 MSS_EXTERNAL_SR SW1C N A SYSRESE...

Page 270: ...e data transfers The configuration of HPDMA is done through the APB interface One of the main applications for which the HPDMA can be used is paging access by the processor The main data is stored in a large DDR space and relevant chunks of this data would be transferred as needed via the HPDMA to the eSRAM where it can be processed faster Figure 120 HPDMA Interfacing With MSSDDR Bridge and AHB Bu...

Page 271: ...requests HPDMA descriptor in a round robin fashion To process each request HPDMA descriptor is configured by an AHB bus matrix master through APB interface The AHB bus matrix master can be Cortex M3 USB Ethernet and Fabric master The HPDMA APB interface is connected on APB_1 which is an AHB to APB bridge as shown in the preceding figure HPDMA then reads data from the source memory and transfers da...

Page 272: ...us registers of the HPDMA controller are accessed through a 32 bit APB slave as shown in the following figure To enable and use HPDMA services the AHB bus matrix master must configure the 32 bit wide descriptor registers There are four descriptors available with the HPDMA controller Each descriptor has the following five registers Source memory address register Destination memory address register ...

Page 273: ...eady signal The AHB master acknowledges and the write buffer controller writes the source memory data to the internal data buffer If the data buffer is full the write buffer controller initiates idle transfers on the AHB bus and asserts ready signal when at least one data buffer is available The write buffer controller pauses the DMA transfers when the descriptor pause bit is enabled and resumes t...

Page 274: ...RESET_CR system register 8 2 1 2 Descriptor Configuration Before configuring each HPDMA channel the round robin weight is specified if needed using the MASTER_WEIGHT_CR register or configuring the AHB bus matrix in Libero SoC To configure each HPDMA descriptor the following registers have to be set Descriptor Control registers Direction bit 1 of HPDMADXCR_REG where X is 0 to 3 Transfer size in byt...

Page 275: ...the bit 19 of Descriptor control register the HPDMA stops the data transfer HPDMA resumes the operation once the pause bit is reset The pending transfers of the source and destination can be read from the Descriptor pending transfer register HPDMADXPTR where X is 0 to 3 HPDMA can service the next descriptor only after the pending transfer of the current descriptor is complete The data transfer com...

Page 276: ...erformance DMA Controller UG0331 User Guide Revision 15 0 242 1 Enable HPDMA by using MDDR in the application as shown in the following figure Figure 124 Enable HPDMA in the Libero SOC Design MSS Configurator ...

Page 277: ...ternal memory configurator as shown in the following figure Figure 125 HPDMA Transfers Data Between DDR Memory and MSS Internal Memory 3 To configure the HPDMA to transfer data between SDR memory and MSS internal memory make the selection in the MSS external memory configurator as shown in the following figure Figure 126 HPDMA Transfers Data Between SDR Memory and MSS Internal Memory ...

Page 278: ...hpdma c and mss_hpdmac h which provides a set of functions for controlling the MSS HPDMA transfers The mss_hpdma firmware driver can also be downloaded from the Microsemi firmware catalog The following table shows the list of APIs for HPDMA For more information on the APIs refer to the SmartFusion2_MSS_HPDMA_Driver_UG shown in the preceding figure Table 148 MSS HPDMA APIs Category API Description ...

Page 279: ...ory Controller Fabric Interface Controller chapter in the UG0446 SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide 8 3 2 1 Use Model 1 AHB Bus Matrix to MSS DDR Bridge MSS DDR Bridge to AHB Bus Matrix 1 Enable HPDMA by using MDDR or configuring switch and MSSDDR bridge in Libero SoC 2 Initialize the HPDMA using MSS_HPDMA_init 3 Check HPDMAEDR register bits using MSS_HPDMA_get_trans...

Page 280: ...0 Status register HPDMAD0PTR_REG x14 R x00 Descriptor 0 Pending Transfer register HPDMAD1SAR_REG x18 R W x00 Descriptor 1 source memory start address HPDMAD1DAR_REG x1C R W x00 Descriptor 1 destination memory start address HPDMAD1CR_REG x20 R W x00 Descriptor 1 Control register HPDMAD1SR_REG x24 R x00 Descriptor 1 Status register HPDMAD1PTR_REG x28 R x00 Descriptor 1 Pending Transfer register HPDM...

Page 281: ... 2 1 Descriptor 2 is empty and ready for software configuration 1 Descriptor 2 is empty and ready to configure 0 Descriptor 2 is already configured and descriptor transfer is in progress queue At the end of the descriptor transfer either on transfer error or transfer done the HPDMA controller asserts this bit High 3 HPDMAEDR_DCP_EMPTY 3 1 Descriptor 3 is empty and ready for software configuration ...

Page 282: ...it of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID 2 bit of the descriptor 2 Control register is set 7 HPDMAEDR_DCP_CMPLET 3 0 Descriptor 3 transfer complete 1 Descriptor 3 transfer completed successfully 0 Descriptor 3 transfer not completed When the descriptor 3 transfer is completed either with transfer error or transfer done the HPDMA controller asserts this bit High This b...

Page 283: ...R_DCP_ERR 3 0 Descriptor 3 transfer error 1 Descriptor 3 transfer error 0 No descriptor 3 transfer error This bit is asserted High if an error occurs during the descriptor 3 transfer at either source or destination end This bit is cleared on writing 1 to HPDMAICR_CLR_XFR_INT 3 of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID 3 bit of the descriptor 3 control register is set 12 H...

Page 284: ...1 to HPDMAICR_NON_WORD_INT 2 of the HPDMA Interrupt Clear register or when the HPDMACR_DCP_VALID 2 bit of the descriptor 2 Control register is set or when the HPDMACR_DCP_CLR 2 bit of the HPDMA Controller register is set In this case HPDMA will continue the transfer by ignoring the 2 LSBs of the transfer size field 15 HPDMAEDR_DCP_NON_WORD_ERR 3 0 Descriptor 3 non word aligned transfer size error ...

Page 285: ...ress to prevent non word aligned transfers at the start and 2 LSBs 1 0 are masked in the hardware The source address is updated when descriptor transfer is in progress Table 151 HPDMAD0SAR_REG Bit Number Name Reset Value Description 31 0 HPDMASAR_DCP0_SRC_ADRS 0x00 Descriptor 0 source end memory start address Table 152 HPDMAD1SAR_REG Bit Number Name Reset Value Description 31 0 HPDMASAR_DCP1_SRC_A...

Page 286: ...prevent non word aligned transfers at the start and 2 LSBs 1 0 are masked in the hardware The destination address will be updated in the same field when the descriptor transfer is in progress Table 155 HPDMAD0DAR_REG Bit Number Name Reset Value Description 31 0 HPDMADAR_DCP0_DST_ADRS 0x00 Descriptor 0 destination end memory start address Table 156 HPDMAD1DAR_REG Bit Number Name Reset Value Descrip...

Page 287: ... to MSS DDR bridge 1 MSS DDR bridge to AHB bus matrix 18 HPDMACR_DCP_CLR 0 0 When this bit is set HPDMA clears the descriptor 0 fields HPDMA terminates the current transfer and reset descriptor status and control registers This bit is always read back as zero 19 HPDMACR_DCP_PAUSE 0 0 1 HPDMA pauses descriptor 0 transfers does idle transfers 0 HPDMA resumes descriptor 0 transfers from where they ha...

Page 288: ...rix to MSS DDR bridge 1 MSS DDR bridge to AHB bus matrix 18 HPDMACR_DCP_CLR 1 0 When this bit is set HPDMA clears the descriptor 1 fields HPDMA terminates the current transfer and resets descriptor status and control registers This bit is always read back as zero 19 HPDMACR_DCP_PAUSE 1 0 1 HPDMA pauses Descriptor 1 transfers does idle transfers 0 HPDMA resumes descriptor 1 transfers from where the...

Page 289: ... to MSS DDR bridge 1 DDR bridge to AHB bus matrix 18 HPDMACR_DCP_CLR 2 0 When this bit is set HPDMA clears the descriptor 2 fields HPDMA terminates the current transfer and reset descriptor status and control registers This bit is always read back as zero 19 HPDMACR_DCP_PAUSE 2 0 1 HPDMA pauses the descriptor 2 transfers does idle transfers 0 HPDMA resumes descriptor 2 transfers from where they ha...

Page 290: ...S DDR bridge 1 MSS DDR bridge to AHB bus matrix 18 HPDMACR_DCP_CLR 3 0 When this bit is set HPDMA clears the descriptor 3 fields HPDMA terminates the current transfer and resets descriptor status and control registers This bit is always read back as zero 19 HPDMACR_DCP_PAUSE 3 0 1 HPDMA pauses the descriptor 3 transfers does idle transfers 0 HPDMA resumes the descriptor 3 transfers from where they...

Page 291: ...er error 1 Descriptor 0 transfer error 0 No error at destination end during descriptor 0 transfer This bit clears on writing 1 to HPDMAICR_CLR_XFR_INT 0 of the descriptor 0 Interrupt Clear register 31 4 Reserved 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation...

Page 292: ...DMASR_DCP_CMPLET 2 0 Descriptor 2 transfer complete 1 Descriptor 2 transfer completed successfully 0 Descriptor 2 transfer not completed This bit clears on writing 1 to HPDMAICR_CLR_XFR_INT 2 of the descriptor 2 Control register 2 HPDMASR_DCP_SERR 2 0 Descriptor 2 source transfer error 1 Descriptor 2 transfer error occurred at source end 0 No error at source end during descriptor 2 transfer This b...

Page 293: ...tor 3 transfer error 0 No error at destination end during descriptor 3 transfer This bit clears on writing 1 to HPDMAICR_CLR_XFR_INT 3 of the descriptor 3 Interrupt Clear register 31 4 Reserved 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Table 167 HPDMAD0...

Page 294: ...or 1 At the end of the transfer zero in this register indicates the successful transfer and a non zero value indicates error occurrence at the destination during descriptor 1 transfer Table 169 HPDMAD2PTR_REG Bit Number Name Reset Value Description 15 0 HPDMAPTR_D2_SRC_PNDNG 0 Descriptor 2 source pending transfers in words This register indicates the internal transfer size counter corresponding to...

Page 295: ...icates error occurrence at the destination during descriptor 3 transfer Table 171 HPDMAICR_REG Bit Number Name Reset Value Description 0 HPDMAICR_CLR_XFR_INT 0 0 When this bit is set HPDMA clears the following register bits Descriptor 0 Status register HPDMASR_DCP_CMPLET 0 HPDMASR_DCP_DERR 0 HPDMASR_DCP_SERR 0 HPDMA Empty Descriptor register HPDMAEDR_DCP_NON_WORD_ERR 0 1 HPDMAICR_CLR_XFR_INT 1 0 W...

Page 296: ... should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Table 172 HPDMADR_REG Bit Number Name Reset Value Description 0 HPDMADR_BFR_EMPTY 1 Data buffer is empty HPDMA controller initiates idle transfers on the destination memory end 1 Data buffer is empty 0 Data Buffer is not ...

Page 297: ...N_CST_DBG 3 0 0 Round robin FSM current state 0001 D0 0010 D1 0100 D2 1000 D3 27 26 HPDMADR_DMA_CST_DBG 1 0 0 DMA controller FSM current state 01 IDLE 10 RUN 31 28 Reserved 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Table 173 SYSREG Control Registers Reg...

Page 298: ...rocessor For example the firmware could direct the PDMA to transfer the next 1 000 characters received on one of the MMUARTs to eSRAM and notify the processor when ready 9 1 Features Up to 8 DMA channels Ping pong mode support Channels priority designations Memory to memory DMA capable Interrupt capability Figure 129 PDMA Interfacing with AHB Bus Matrix AHB Bus Matrix eSRAM_0 System Controller Cac...

Page 299: ...t APB slave used for configuring the PDMA DMA operations do not occur on the APB bus interface of the PDMA The PDMA performs single cycle accesses on the AHB interface only and Burst mode is not supported AHB Bus Matrix 10x7 Cache Controller S D IC ARM Cortex M3 Processor PDMAINTERRUPT DMA_READY_1 1 0 DMA_READY_0 1 0 RxRDY and TxRDY RxRDY and TxRDY RxRDY and TxRDY OUTREADY and INREADY SPIRXAVAIL a...

Page 300: ... when reading from a peripheral holding register single address and writing to memory incrementally many addresses Sixteen possible channels are available to the PDMA as listed below Only eight are used simultaneously MMUART_0 to any MSS memory mapped location Any MSS memory mapped location to MMUART_0 MMUART_1 to any MSS memory mapped location Any MSS memory mapped location to MMUART_1 SPI_0 to a...

Page 301: ...ll use a buffer A when channel0 buffer B transfer count reaches 0 Write to Channel_0_BUFFER_A_TRANSFER_COUNT DMA will use a buffer A when channel0 buffer B transfer count reaches 0 Write to Channel_0_BUFFER_A_SRC_ADDR Write to Channel_0_BUFFER_A_DST_ADDR Write to Channel_0_BUFFER_B_SRC_ADDR Write to Channel_0_BUFFER_B_DST_ADDR If interrupt on the DMA channel buffer A If interrupt on the DMA channe...

Page 302: ...m used to service the channels based on the priority as shown in Figure 130 page 265 By default all channels have equal priority To configure the PDMA channel priority RATIO_HIGH_LOW register must be configured by the AHB bus matrix master The RATIOHILO field in the RATIO_HIGH_LOW register indicates the ratio of high priority requests to low priority requests For example a RATIOHILO value of 3 1 m...

Page 303: ... logic instantiated in the FPGA To determine transfer complete interrupt for each channel the BUFFER_STATUS_x register bits 1 0 has to be monitored The bit 7 and bit 8 of CHANNEL_x_CONTROL register are used to clear the transfer complete interrupts of the channel 9 2 4 Details of Operations After initialization the PDMA is ready to function in any one of following transfer modes Peripheral to Memo...

Page 304: ...TROL register is an 8 bit binary coded field used to define for each DMA channel how long to wait in M3_CLKs after each DMA transfer cycle before interpreting the ready signal for that DMA channel as representing a new request A suitable value for WRITE_ADJ depends on the target of the DMA transfer The following steps describe how to select the values 1 The WRITE_ADJ value of 10 can be provided as...

Page 305: ... This following sections describe how to use the PDMA in an application 9 3 1 Design Flow The following steps are used to enable the PDMA in the application 1 Enable PDMA by using the MSS configurator in the application as shown in the following figure Figure 132 Enable PDMA ...

Page 306: ...s shown in the following figure Figure 133 PDMA AHB Bus Master Matrix Configuration 3 To configure the PDMA to transfer data between fabric peripherals associated on FIC_0 and FIC_1 and MSS memories select the PDMA configurator as shown in the following figure Figure 134 PDMA Transfers Data Between FIC and MSS Memory ...

Page 307: ...ent in the Libero SoC design flow window to generate the SoftConsole Firmware Project The SoftConsole folder contains the mss_pdma firmware driver The firmware driver mss_pdma mss_pdma c and mss_pdma h which provides a set of functions for controlling the MSS PDMA transfers can also be downloaded from the Microsemi firmware catalog the following table lists the APIs for PDMA For more information o...

Page 308: ...gure Transfer type Selection of the peripheral and direction if peripheral to memory transfer is selected Transfer size data width Source and destination address increment Channel priority Wait states WRITE_ADJ DMA transfer and control PDMA_start Starts PDMA transfer PDMA_load_next_buffer Loads with next buffer of data PDMA_status Gets the status of PDMA transfer Interrupt control functions PDMA_s...

Page 309: ...ATUS 0x04 R 0 Indicates when buffers have drained CHANNEL_x_CONTROL X 0 0x20 R W 0 Channel 0 Control register CHANNEL_x_STATUS X 0 0x24 R 0 Channel 0 Status register CHANNEL_x_BUFFER_A_SRC_ADDR x 0 0x28 R W 0 Channel 0 buffer A source address CHANNEL_x_BUFFER_A_DST_ADDR x 0 0x2C R W 0 Channel 0 buffer A destination address CHANNEL_x_BUFFER_A_TRANSFER_COUNT x 0 0x30 R W 0 Channel 0 buffer A transfe...

Page 310: ...CHANNEL_3_BUFFER_A_DST_ADDR 0x8C R W 0 Channel 3 buffer A destination address CHANNEL_3_BUFFER_A_TRANSFER_COUNT 0x90 R W 0 Channel 3 buffer A transfer count CHANNEL_3_BUFFER_B_SRC_ADDR 0x94 R W 0 Channel 3 buffer B source address CHANNEL_3_BUFFER_B_DST_ADDR 0x98 R W 0 Channel 3 buffer B destination address CHANNEL_3_BUFFER_B_TRANSFER_COUNT 0x9C R W 0 Channel 3 buffer B transfer count CHANNEL_4_CON...

Page 311: ...el 6 buffer A destination address CHANNEL_6_BUFFER_A_TRANSFER_COUNT 0xF0 R W 0 Channel 6 buffer A transfer count CHANNEL_6_BUFFER_B_SRC_ADDR 0xF4 R W 0 Channel 6 buffer B source address CHANNEL_6_BUFFER_B_DST_ADDR 0xF8 R W 0 Channel 6 buffer B destination address CHANNEL_6_BUFFER_B_TRANSFER_COUNT 0xFC R W 0 Channel 6 buffer B transfer count CHANNEL_7_CONTROL 0x100 R W 0 Channel 7 Control register ...

Page 312: ...ify write operation 15 CH7BUFB 0 If CH_COMP_B for channel 7 is set and if BUF_B_SEL for channel 7 is clear this bit is asserted 14 CH7BUFA 0 If CH_COMP_A for channel 7 is set and if BUF_A_SEL for channel 7 is clear this bit is asserted 13 CH6BUFB 0 If CH_COMP_B for channel 6 is set and if BUF_B_SEL for channel 6 is clear this bit is asserted 12 CH6BUFA 0 If CH_COMP_A for channel 6 is set and if BU...

Page 313: ...r another transfer This is typically used to ensure that a posted write has fully completed to the peripheral in cases where the peripheral is running at a lower clock frequency than the PDMA However it may also be used to allow the PDMA to take account of internal latencies in the peripheral where the ready status of a FIFO may not be available for a number of clock ticks after a read or write du...

Page 314: ...ripheral ready signal associated with this DMA channel is interpreted as initiating transfers either from memory to the peripheral or vice versa Table 181 PERIPHERAL_SEL Bit 26 Bit 25 Bit 24 Bit 23 Function 0 0 0 0 From UART_0 receive to any MSS memory mapped location 0 0 0 1 From any MSS memory mapped location to UART_0 transmit 0 0 1 0 From UART_1 receive to any MSS memory mapped location 0 0 1 ...

Page 315: ...H_COMP_A 0 Asserts when this channel completes its DMA Cleared by writing to CLR_COMP_A bit 8 in CHANNEL_x_CONTROL register for this channel If INTEN is set for this channel the assertion of CH_COMP_A causes PDMAINTERRUPT to assert Table 183 CHANNEL_x_BUFFER_A_SRC_ADDR Bit Number Name Reset Value Description 31 0 BUF_A_SRC 0 Start address from which data is to be read during the next DMA transfer ...

Page 316: ... is to be read during the next DMA transfer cycle If PERIPHERAL_DMA 1 and DIR 0 this value is not incremented from one DMA transfer cycle to the next Otherwise it is always incremented by an amount corresponding to the TRANSFER_SIZE for this channel Table 187 CHANNEL_x_BUFFER_B_DST_ADDR Bit Number Name Reset Value Description 31 0 BUF_B_DST 0 Start address from which data is to be write during the...

Page 317: ... located in the SYSREG section of the user s guide and are listed here for convenience Refer to System Register Block page 670 for a detailed description of each register and associated bits Table 189 SYSREG Control Registers Register Name Register Type Flash Write Protect Reset Source Description SOFT_RESET_CR RW P Bit SYSRESET_N Soft reset control MASTER_WEIGHT1_CR RW P Register SYSRESET_N Confi...

Page 318: ...ltipoint capabilities Supports four direct memory access DMA channels for data transfers Support for high bandwidth isochronous ISO pipe enabled endpoints Hardware selectable option for 8 bit 4 bit low pin interface LPI interface Supports the following two hardware interfaces to external USB physical layer PHY UTMI Level 3 transceiver interface with fabric ULPI link interface direct to inputs outp...

Page 319: ...ion of the USB OTG controller 10 2 1 Architecture Overview The following block diagram highlights the main blocks in the USB OTG controller The USB OTG controller is interfaced through the advanced high performance bus AHB matrix in the MSS The SmartFusion2 USB OTG provides two interfaces ULPI and UTMI to connect to the external PHY Following are the main component blocks in the USB OTG controller...

Page 320: ...1 3 Endpoints EP Control Logic and RAM Control Logic These two blocks constitute buffer management for the data buffers in Host mode and in Device mode This block manages end point buffers and their properties called pipes which are defined by control bulk interrupt and ISO data transfers Data buffers in device mode endpoints and in host mode are supported by the SECDED block which will automatica...

Page 321: ...2 2 1 ULPI UTMI Low Pin Interface I O Interface The SmartFusion2 USB OTG controller communicates with the external ULPI PHY device using this interface As shown in the following figure the ULPI interface is routed through the MSIO ports These I Os are dedicated to the USB ULPI interface only When the USB OTG controller is selected during configuration these I Os are not multiplexed with other peri...

Page 322: ... 1692 smartfusion2 documentation PPAT documents are grouped under the section Pinout Packaging in the above mentioned site 10 2 2 2 UTMI USB 2 0 Transceiver Macrocell Interface Interface This is the external interface connecting the SmartFusion2 USB OTG controller to an off chip UTMI PHY device For UTMI interface all the interface signals are routed through the FPGA fabric on to the MSIOs Table 19...

Page 323: ...ver LS packet UTMI_TERMSEL Out Termination select When 0 high speed termination is enabled when 1 full speed termination is enabled May be used to switch the pull up resistor on D UTMI_VBUSVALID In Compares VBus to selected VBus valid threshold required to be between 4 4 V and 4 75 V 1 Above the VBus valid threshold 0 Below the VBus valid threshold UTMI_AVALID In Compares VBus to session valid thr...

Page 324: ...n the D line Low when the USB controller is operating as a peripheral High when USB controller is operating as a host UTMI_DMPULLDOWN Out Enables a pull down resistor within the transceiver on the D line Needs to be high when the USB controller is used for point to point communications UTMI_IDDIG In Indicates USB controller connector type High B type Low A type UTMI_IDPULLUP Out Enables for IDDIG ...

Page 325: ...for all the transactions in the bus In this mode the USB OTG controller enumerates the external device that is connected Based on the USB firmware class drivers and application code implemented in the SmartFusion2 device if the connected device USB class is supported the SmartFusion2 USB OTG controller exchanges the data with the connected device as per the application requirement of the USB funct...

Page 326: ...Peripheral mode the UTMI compliant PHY that is used alongside the USB controller can be switched between normal mode and non driving mode by setting clearing the Soft Conn bit in POWER_REG 0x40043001 START STOP Initialization 1 Disable initialize the Watchdog Timer 2 Configure the GPIO for keeping the PHY out of reset 3 Register the callback functions and ISRs 4 Clear and enable the interrupts 5 I...

Page 327: ...e USB controller register Based on the type of the plug connected to the PHY through the USB OTG receptacle the controller plays a role as either the USB device or the USB host If the plug device with type microA is connected the corresponding interrupt generated to the USB controller and the firmware configures the USB OTG controller into the USB Host mode If the plug device with microB is connec...

Page 328: ...Fusion2 device through the external PHY the USB controller will take the role of the host and go into Host mode Entering into device mode If the micro B end of the cable is plugged in the USB controller will go instead into Peripheral mode and Host mode bit will be set to 0 Changing the role which out swapping the cable ends Where the USB controller is connected to a single device that contains a ...

Page 329: ...and enable the interrupts 5 In this mode USB OTG microAB receptacle on board is connected to PHY Wait for the connection interrupt 1 Set the USB Controller in Host mode 2 Enumerates the device Device Connected type A Host supports the device class ON Class specific and application code execution START ISR to handle the USB interrupts in OTG mode 1 Connect Disconnect Interrupt 2 Endpoint 0 Interrup...

Page 330: ...SB OTG Controller Suspend Resume Operations With the introduction of link power management LPM there are two basic methods for the USB controller to be suspended and resumed These two methods are demonstrated in the basic LPM transaction diagram as shown in the following figure Figure 145 LPM State Transition Diagram The procedure in which the controller is suspended and resumed depends on whether...

Page 331: ...e it must clear the Suspend mode bit and set the resume bit in the POWER_REG and leave it set for 20 ms while the resume bit is high the USB controller generates resume signaling on the bus After 20 ms the Cortex M3 processor or fabric master should clear the resume bit at which point the frame counter and transaction scheduler are started Responding to Remote Wake Up If resume signaling is detect...

Page 332: ...tion The USB controller responds with an ACK in this case regardless of the LPMXMT value in LPM_CTRL_REG 0x40043362 Peripheral 3 An interrupt is generated informing software of the response an ACK in this case An ACK response is the indication to the software that the USB controller has suspended Since the primary purpose of LPM is to save power the software will read the LPM_ATTR_REG 0x40043360 t...

Page 333: ...S bit in LPM_CTRL_REG 0x40043362 Host This bit is self clearing This causes resume signaling to be generated on the bus for the time that is currently specified in the HIRD field in LPM_ATTR_REG 0x40043360 Hardware assumes that this value was used in the last LPM transaction that caused the suspend mode 3 After HIRD 10 µs the controller transitions to its normal operational state and is ready for ...

Page 334: ...roject Configure enable disable the SmartFusion2 MSS components as per the application needs using the MSS configurator Configure the USB OTG controller as explained in the following sections Note The MSS USB does not support full behavioral simulation models Refer to SmartFusion2 MSS BFM Simulation User Guide for more information 10 3 1 Libero Settings for USB OTG Configuration USB OTG controller...

Page 335: ...g the USB OTG controller with ULIP PHY the USB MSIO signals are connected to four separate mutually exclusive I O groups USBA USBB USBC and USBD I O In the M2S050 devices only the USBD I O group is available Where in the M2S025 and the M2S010 only the USBA USBB and USBC I O groups are available Based on the SmartFusion2 device selected the I O groups can be selected from the USB configurator Figur...

Page 336: ...abric onto the MSIOs There is no separate I O grouping like the ULPI interface has for the SmartFusion2 device variants to use with UTMI PHY Figure 148 MSS USB Configurator with UTMI Interface Settings 10 3 1 3 External USB PHY Reset Signal Configuration To reset the external USB PHY Microsemi recommends configuring the GPIO port The following figure shows the GPIO settings in the MSS GPIO configu...

Page 337: ...USB configurations using the Libero SoC design software refer to the Libero SoC User Guide in the USB configurations section 10 3 2 Software Firmware USB Class Specific Code and Application Code The embedded software flow for the USB applications vary based on the USB OTG controller role as Host Device The following sections describe the embedded software flow for both the USB Device mode and the ...

Page 338: ...ions device Microsemi recommends to refer these drivers to implement the USB device application as per the requirements Figure 151 Firmware Catalog with MSS USB Firmware Drivers and Sample Class Drivers For more implementation details on the USB Protocol for the USB Device mode refer to the USB 2 0 specifications Microsemi provides the device drivers for the USB OTG controller for SmartFusion2 and...

Page 339: ... the USB host to identify the device MSS_USB_core_device_get_address Returns the address set for the MSS USB in the Device mode This value generally is assigned by the USB host to identify the device MSS_USB_core_device_force_resume Forces the MSS USB core to exit Suspend mode and generate resume signaling when operating in Device mode MSS_USB_core_device_set_isoupdate Forces ISO endpoint from the...

Page 340: ...ted MSS_USB_device_cep_clr_error Clears the stall condition on previously stalled control endpoint MSS_USB_device_tx_ep_configure Configures the transmit EP USB IN Transfers as per the provided parameters MSS_USB_device_rx_ep_configure Configures the receive EP USB OUT Transfers as per the provided parameters MSS_USB_device_rx_ep_read_prepare Prepares receive EP for receiving data packets USB OUT ...

Page 341: ...dpoint The endpoint on which data is received is indicated by parameter num The parameter status indicates error status of the receive transaction A non zero status value indicates that there was error in last receive transaction The rx_count parameter indicates the number of bytes received in the last receive transaction uint8_t usb_class_cep_datain uint8_t status This function is called when dat...

Page 342: ...gisters in the USB controller In addition System Registers that are applicable to USB are described in this section This provides programmers information for firmware development Microsemi recommends using the drivers provided in the tool set for application development The Register set in the USB controller consists of the following categories Common Registers Provide control and status for the U...

Page 343: ...oint0 and EP1 EP2 EP3 and EP4 have corresponding enable bits from bit 0 to bit 4 of this register A value of 1 indicates the interrupt is enabled RX_IRQ_EN_REG 0x40043008 0x40043008 16 0x1E Provides interrupt enables for interrupts in RX_IRQ_REG The endpoints EP1 EP2 EP3 and EP4 have corresponding enable bits from bit 1 to bit 4 of this register A value of 1 indicates the interrupt is enabled USB_...

Page 344: ...l mode Also this bit only affects endpoints performing ISO transfers 6 Soft Conn 0 If the soft connect disconnect feature is enabled the USB D D lines are enabled when this bit is set by the Cortex M3 processor or fabric master and tristated when this bit is cleared by the Cortex M3 processor or fabric master Only valid in Peripheral mode 5 HS Enab 1 When set by the CPU the USB controller negotiat...

Page 345: ...de It is cleared when the Cortex M3 processor or fabric master reads the interrupt register or sets the resume bit above 0 Enable SuspendM 0 Set by the Cortex M3 processor or fabric master to enable the SUSPENDM output Table 201 TX_IRQ_REG 0x40043002 Bit Number Name Reset Value Function 15 5 Reserved N A N A 4 EP4 Tx 0 Transmit endpoint 4 interrupt 3 EP3 Tx 0 Transmit endpoint 3 interrupt 2 EP2 Tx...

Page 346: ... 1 EP1 RxEn 1 Receive endpoint 1 interrupt enable 0 Reserved 0 Always returns zero Table 205 USB_IRQ_REG 0x4004300A Bit Number Name Reset Value Function 7 VBus Error 0 Set when VBus drops below the VBus valid threshold during a session Only valid when the USB controller is an A device 6 Sess Req 0 Set when session request signaling has been detected Only valid when the USB controller is an A devic...

Page 347: ...IRQ_REG 4 CoEn 0 Interrupt Enable for corresponding bit 4 Conn in USB_IRQ_REG 3 SofEn 0 Interrupt Enable for corresponding bit 3 SOF in USB_IRQ_REG 2 ReBaEn 1 Interrupt Enable for corresponding bit 2 Reset Babble in USB_IRQ_REG 1 ReEn 1 Interrupt Enable for corresponding bit 1 Resume in USB_IRQ_REG 0 SuEn 0 Interrupt Enable for corresponding bit 0 Suspend in USB_IRQ_REG Table 207 FRAME_REG 0x40043...

Page 348: ...ve or to force the USB controller into Full speed mode when it receives a USB reset 4 Force_HS 0 The Cortex M3 processor or fabric master sets this bit either in conjunction with bit 7 above or to force the USB controller into High speed mode when it receives a USB reset 3 Test_Packet 0 High speed mode The Cortex M3 processor or fabric master sets this bit to enter Test_Packet test mode In this mo...

Page 349: ... endpoint0 Index register set to select endpoints 1 4 The interpretation of the register depends on whether the USB controller is acting as a peripheral or a host The value returned when the register is read reflects the status attained for example as a result of writing to the register RX_MAX_P_REG 0x40043014 16 RW 0 Defines the maximum amount of data that can be transferred through the selected ...

Page 350: ...dpoints 1 4 NAK_LIMIT0_REG 0x4004301B 5 RW 0 Sets the NAK response timeout on endpoint 0 Index register set to select endpoint 0 TX_INTERVAL_REG 0x4004301B 8 RW 0 Sets the polling interval for interrupt ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint Index register set to select endpoints 1 4 only RX_TYPE_REG 0x4004301C 8 RW 0 Sets the transaction prot...

Page 351: ... each transaction is 1 024 bytes so this allows up to 3 072 bytes to be transmitted in each microframe For ISO transfers in Full speed mode or if high bandwidth is not enabled bits 11 and 12 are ignored The value written to bits 10 0 multiplied by m in the case of high bandwidth ISO transfers must match the value given in the wMaxPacketSize field of the standard endpoint descriptor for the associa...

Page 352: ...n this bit is set The Cortex M3 processor or fabric master clears this bit by setting the ServicedRxPktRdy bit bit 6 of this register Table 214 CSR0L_REG Host Bit Number Name Reset Value Function 7 NAK Timeout 0 This bit is set when endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLimit0 register The Cortex M3 processor or fabric master should clea...

Page 353: ...CSR0H_REG Host Bit Number Name Reset Value Function 7 4 Reserved N A 3 Dis Ping 0 The Cortex M3 processor or fabric master writes a 1 to this bit to instruct the USB controller not to issue PING tokens in data and status phases of a high speed control transfer for use with devices that do not respond to PING 2 Data Toggle Write Enable 0 The Cortex M3 processor or fabric master writes a 1 to this b...

Page 354: ...nd an interrupt is generated It Mmay be set simultaneously with TxPktRdy to abort the packet that is currently being loaded into the FIFO FlushFIFO should only be used when TxPktRdy is set At other times it may cause data to be corrupted Also note that if the FIFO is double buffered FlushFIFO may need to be set twice to completely clear the FIFO 2 UnderRun 0 The controller sets this bit if an IN t...

Page 355: ...ushed The Cortex M3 processor or fabric master should clear this bit Valid only when the endpoint is operating in Bulk or Interrupt mode 1 FIFONotEmpty 0 The controller sets this bit when there is at least 1 packet in the transmit FIFO 0 TxPktRdy 0 The Cortex M3 processor or fabric master sets this bit after loading a data packet into the FIFO It is cleared automatically when a data packet has bee...

Page 356: ... set manually Should not be set for high bandwidth ISO endpoints or high bandwidth interrupt endpoints 6 Reserved N A 5 Mode 0 The Cortex M3 processor or fabric master sets this bit to enable the endpoint direction as transmit and clears the bit to enable it as receive This bit only has effect where the same endpoint FIFO is used for both transmit and receive transactions 4 DMAReqEnab 0 The Cortex...

Page 357: ...ber of such transactions that can take place in a single microframe If either bit 11 or bit 12 is non zero the USB controller automatically combines the separate USB packets received in any microframe into a single packet within the receive FIFO The maximum payload for each transaction is 1 024 bytes so this allows up to 3 072 bytes to be received in each microframe For ISO transfers in Full speed...

Page 358: ... twice to completely clear the FIFO 3 DataError 0 This bit is set when RxPktRdy bit 0 of this register is set if the data packet has a CRC or bit stuff error It is cleared when RxPktRdy is cleared This bit is only valid when the endpoint is operating in ISO mode In Bulk mode it always returns zero 2 OverRun 0 This bit is set if an OUT packet cannot be loaded into the receive FIFO The Cortex M3 pro...

Page 359: ...d The Cortex M3 processor or fabric master should clear this bit This bit is only valid when the Rx endpoint is operating in Bulk or Interrupt mode In ISO mode it always returns zero 1 FIFOFull 0 This bit is set when no more packets can be loaded into the receive FIFO 0 RxPktRdy 0 This bit is set when a data packet has been received The Cortex M3 processor or fabric master should clear this bit wh...

Page 360: ... Packet Sizes that will Clear RxPktRdy 0 RXMaxP 64 bytes RxMaxP RxMaxP RxMaxP 1 RxMaxP 2 RxMaxP 3 3 RXMaxP 63 bytes RxMaxP 1 RxMaxP RxMaxP 1 RxMaxP 2 2 RXMaxP 62 bytes RxMaxP 2 RxMaxP RxMaxP 1 1 RXMaxP 61 bytes RxMaxP 3 RxMaxP Table 226 RX_CSRH_REG Host Bit Number Name Reset Value Function 7 AutoClear 0 If the Cortex M3 processor or fabric master sets this bit the RxPktRdy bit bit 0 in RXCSRL_REG ...

Page 361: ...value written to this bit is ignored 0 IncompRx 0 This bit is set in a high bandwidth ISO interrupt transfer if the packet in the receive FIFO is incomplete because parts of the data were not received It is cleared when RxPktRdy bit 0 in RXCSRL_REG is cleared In anything other than ISO transfer this bit always returns 0 Table 227 COUNT0_REG Bit Number Name Reset Value Function 6 0 Endpoint0 Rx Cou...

Page 362: ...set Value Function 4 0 Endpoint0 NAK Limit m 0 Sets the number of frames microframes high speed transfers after which endpoint 0 should timeout on receiving a stream of NAK responses Equivalent settings for other endpoints can be made through their TX_INTERVAL_REG and TX_INTERVAL_REG registers The number of frames microframes selected is 2 m 1 where m is the value set in the register valid values ...

Page 363: ...ler 01 High 10 Full 11 Low When the core is not configured with the multipoint option these bits should not be accessed 5 4 Protocol 0 The Cortex M3 processor or fabric master should set this to select the required protocol for the receive endpoint 00 Control 01 ISO 10 Bulk 11 Interrupt 3 0 Target Endpoint Number 0 The Cortex M3 processor or fabric master should set this value to the endpoint numb...

Page 364: ...237 FIFO_SIZE_REG Bit Number Name Reset Value Function 7 4 Rx FIFO Size N A Returns the sizes of the FIFOs associated with the selected additional transmit receive endpoints The lower nibble 3 0 encodes the size of the selected transmit endpoint FIFO the upper nibble 7 4 encodes the size of the selected receive endpoint FIFO Values of 3 13 correspond to a FIFO size of 2n bytes 8 8 192 bytes If an ...

Page 365: ...nction 31 0 Epx_TxRxDataAcc 0 Address of endpointx to write data into transmit FIFO or read from receive FIFO The value of x can be 0 1 2 3 or 4 The values of YZ would be differ with the register name 1 EP0_FIFO_REG 0x40043020 2 EP1_FIFO_REG 0x40043024 3 EP2_FIFO_REG 0x40043028 4 EP3_FIFO_REG 0x4004302C 5 EP4_FIFO_REG 0x40043030 Table 240 Additional Control and Status Registers OTG Dynamic FIFO an...

Page 366: ...n successive writes to the VControl register must therefore be Hc 4Xc to ensure that the value is not corrupted while it is being synchronized to the XCLK domain VBUS_CSR_REG read only 0x40043068 0x0068 8 R VStatus VStatus is optionally a UTMI PHY vendor register UTMI specification defines an 8 bit VStatus register The VSTATUS input bus is sampled once every 6 XCLK cycles The latency between the V...

Page 367: ...been detected being connected to the port Only valid in Host mode 4 3 Vbus 1 0 0 These read only bits encode the current VBus level as given in Table 242 page 334 2 Host Mode 0 This read only bit is set when the USB controller is acting as a host 1 Host Req 0 When set the USB controller initiates the host negotiation when Suspend mode is entered It is cleared when host negotiation is completed B d...

Page 368: ...s have been read to an endpoint This is late mode 1 DMA_REQ signal for all OUT endpoints is deasserted when MAXP 8 TX_MAX_P_REG 8 bytes have been read to an endpoint This is early mode Table 244 TX_FIFO_SIZE_REG 0x40043062 Bit Number Name Reset Value Function 4 DPB 0 Defines whether double packet buffering is supported When 1 double packet buffering is supported When 0 only single packet buffering...

Page 369: ...e allowed for before any splitting within the FIFO of bulk high bandwidth packets prior to transmission 00 00 8 Bytes 0 001 16 Bytes 0010 32 Bytes 0011 64 Bytes 0100 128 Bytes 0101 256 Bytes 0110 512 Bytes 0111 1 024 Bytes 1000 2 048 Bytes 1001 4 096 Bytes If DPB 0 the FIFO will also be this size if DPB 1 the FIFO will be twice this size Table 246 TX_FIFO_ADD_REG 0x40043064 Bit Number Name Reset V...

Page 370: ...Reserved N A 12 0 AD 12 0 0 Start address of the receive endpoint FIFO in units of 8 bytes as given in Table 247 page 336 Table 249 VBUS_CSR_REG write only 0x40043068 Bit Number Name Reset Value Function 3 0 Vcontrol 0 Vendor specific control data Table 250 VBUS_CSR_REG read only 0x40043068 Bit Number Name Reset Value Function 7 0 Vstatus 0 Vendor specific status data Table 251 HW_VERSION_REG 0x40...

Page 371: ... 0 This register shows the unmasked value of the possible interrupt sources ULPI_DATA_REG 0x40043074 0x40043074 8 R 0 Contains the data associated with register reads writes conducted through the ULPI interface ULPI_ADDR_REG 0x40043075 0x40043075 8 R 0 Contains the address of the register being read written through the ULPI interface ULPI_REG_CTRL 0x40043076 0x40043076 8 R 0 Contains control and s...

Page 372: ...rnal charge pump Table 254 ULPI_CARKIT_CTRL_REG 0x40043071 Bit Number Name Reset Value Function 7 6 Reserved N A Reserved N A 5 CarKitActiveEnd 0 Set by link when CarKitActive bit 1 of this register is cleared This bit must be cleared by software Signifies that the USB controller s synchronous USB mode has been entered 4 RxCmdEvent 0 Set by link when a RxCmd has been latched This bit must be clear...

Page 373: ...ntEn 0 Assert MC_NINT if RegInt ULPI_IRQ_SRC_REG bit0 is set To clear MC_NINT the software must clear ULPIRegCmplt ULPI_REG_CTRL bit1 Table 256 ULPI_IRQ_SRC_REG 0x40043073 Bit Number Name Reset Value Function 7 4 Reserved N A 3 RxCmdInt 0 Asserted if RxCmdEvent ULPI_CARKIT_CTRL_REG bit4 is set To clear the interrupt the software must clear RxCmdEvent 2 ActiveEndInt 0 Asserted if CarKitActiveEnd UL...

Page 374: ...A 2 ULPIRdnWr 0 Set by software for register read access Cleared by software for register write access 1 ULPIRegCmplt 0 Set by link when register access is complete This bit must be cleared by software 0 ULPIRegReq 0 Set by software to initiate register access This is cleared when ULPIRegCmplt bit 1 of this register is set Table 260 ULPI_RAW_DATA_REG 0x40043077 Asynchronous Bit Number Name Reset V...

Page 375: ...ints 0 The number of transmit endpoints implemented in the design Table 264 RAM_INFO_REG 0x40043079 Bit Number Name Reset Value Function 7 4 DMAChans 0 The number of DMA channels implemented in the design 3 0 RamBits 0 The width of the RAM address bus Table 265 LINK_INFO_REG 0x4004307A Bit Number Name Reset Value Function 7 4 WTCON 0x5 Sets the wait to be applied to allow for the connect disconnec...

Page 376: ... new transactions in units of 533 3 ns The default setting corresponds to 63 46 μs Table 269 LS_EOF1_REG 0x4004307E Bit Number Name Reset Value Function 7 0 LS_EOF1 0x72 For low speed transactions Sets the time before EOF to stop beginning new transactions in units of 1 067 μs The default setting corresponds to 121 6 μs Table 270 SOFT_RESET_REG 0x4004307F Bit Number Name Reset Value Function 7 2 R...

Page 377: ...mount of data that can be transferred through receive endpoint0 in a single operation EP0_RX_CSR_REG 0x0106 16 R 0 Provides control and status bits for transfers through the receive endpoint0 EP0_RX_COUNT_REG 0x0108 16 R 0 Holds the number of data bytes in the packet currently in line to be read from the endpoint0 receive FIFO If the packet was transmitted as multiple bulk packets the number given...

Page 378: ...the combined packet EP1_TX_TYPE_REG 0x011A 8 W 0 Reads the number of bytes to be read from peripheral endpoint1 transmit FIFO EP1_TX_INTERVAL_REG 0x011B 8 RW 0 Sets the polling interval for interrupt ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint1 EP1_RX_TYPE_REG 0x011C 8 RW 0 Sets the transaction protocol speed and peripheral endpoint number for the ...

Page 379: ...ut on bulk transactions for host receive endpoint2 EP2_FIFO_SIZE_REG 0x012E 8 R Returns the configured size of the endpoint2 receive FIFO and transmit FIFOs Table 274 Endpoint3 Control and Status Registers Register Name Address Offset from 0x40043000 Width R W Type Reset Value Description EP3_TX_MAX_P_REG 0x0130 16 RW 0 Maximum packet size for host transmit endpoint3 EP3_TX_CSR_REG 0x0132 16 R 0 P...

Page 380: ... amount of data that can be transferred through receive endpoint4 in a single operation EP4_RX_CSR_REG 0x0146 16 R 0 Provides control and status bits for transfers through the receive endpoint4 EP4_RX_COUNT_REG 0x0148 16 R 0 Holds the number of data bytes in the packet currently in line to be read from the endpoint4 receive FIFO If the packet is transmitted as multiple bulk packets the number give...

Page 381: ...ode 1 Table 277 EPx_RX_COUNT_REG Bit Number Name Reset Value Function 13 0 EPx_Rx Count 0 Holds the number of data bytes in the packet currently in line to be read from the receive FIFO If the packet is transmitted as multiple bulk packets the number given will be for the combined packet The value returned changes as the FIFO is unloaded and is only valid while RxPktRdy bit0 in RX_CSRL_REG is set ...

Page 382: ...ocessor or fabric master should set this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during device enumeration Table 280 EPx_TX_INTERVAL_REG Bit Number Name Reset Value Function 7 0 EPx_Tx Polling Interval NAK Limit m 0 Defines the polling interval for endpointx transmit for interrupt and ISO transfers For bulk endpoints this register s...

Page 383: ...imeout on receiving stream of NAK responses The value that is set defines a number of frames microframes high speed transfers as given in Table 233 page 329 Table 283 EPx_FIFO_SIZE_REG Bit Number Name Reset Value Function 7 4 EPx_Rx FIFO Size N A Returns the sizes of the FIFOs associated with endpointx The lower nibble 3 0 encodes the size of the transmit FIFO the upper nibble 7 4 encodes the size...

Page 384: ...RW 0 Indicates which of the transmit endpoints EP0 EP1 EP2 EP3 EP4 have disabled the double packet buffer functionality C_T_UCH_REG 0x40043344 0x0344 16 RW N A Sets the chirp timeout This number when multiplied by 4 represents the number of XCLK cycles before the timeout occurs That is if XCLK is 30 MHz this number represents the number of 133 ns time intervals before the timeout occurs If XCLK is...

Page 385: ...ant Table 285 EPx_RQ_PKT_COUNT_REG 0x40043XYZ Bit Number Name Reset Value Function 15 0 EPx_RqPktCount 0 Sets the number of packets of size MaxP EPx_TX_MAX_P_REG that are to be transferred in a block transfer Only used in Host mode when AutoReq is set This has no effect in Peripheral mode or when AutoReq is not set The value of x can be 0 1 2 3 or 4 The values of XYZ would be differ with the regis...

Page 386: ...lue Function 15 0 C_T_UCH N A Configurable Chirp Timeout timer The default value is 203Ah if the host PHY data width is 16 bits XCLK is 30 MHz and 4074h if the PHY data width is 8 bits XCLK is 60 MHz corresponding to a delay of 1 1 ms Table 289 C_T_HHSRTN_REG 0x40043346 Bit Number Name Reset Value Function 15 0 C_T_HHRSTN N A The delay from the end of high speed resumes signaling to enabling UTM n...

Page 387: ...2 467 8 1 248 2 601 9 1 312 2 734 10 1 376 2 868 11 1 140 3 001 12 1 504 3 134 13 1 568 3 268 14 1 632 3 401 15 1 696 3 534 Table 292 DMA_REGISTER Description Register Name Address Offset from 0x400430 00 Width R W Type Reset Value Description DMA_INT_REG 0x40043200 0x0200 8 R 0 Provides an interrupt for each DMA channel This interrupt register is cleared when read When any bit of this register is...

Page 388: ...his register are read only and cannot be set by the software As the DMA transfer progresses the memory address is incremented as bytes are transferred CH2_DMA_COUNT_REG 0x021C 32 RW 0 Identifies the current DMA count of the transfer for DMA channel 2 The software sets the initial count of the transfer which identifies the entire transfer length As the count progresses this count is decremented as ...

Page 389: ...sferred CH4_DMA_COUNT_REG 0x023C 32 RW 0 Identifies the current DMA count of the transfer for DMA channel 4 Software sets the initial count of the transfer which identifies the entire transfer length As the count progresses this count is decremented as bytes are transferred Table 293 DMA_INT_REG 0x40043200 Bit Number Name Reset Value Function 7 4 Reserved N A 3 CH4_DMA_INTR 0 Channel4 DMA interrup...

Page 390: ...g from the AHB bus matrix originating from the Cortex M3 processor or fabric master This bit is cleared by the software 7 4 DMAEP 0 The endpoint number EP0 EP1 EP2 EP3 EP4 this channel is assigned to 3 DMAIE 0 DMA interrupt enable 2 DMAMODE 0 Selects DMA Transfer mode 0 DMA Mode 0 transfer 1 DMA Mode 1 transfer 3 DMA_DIR 0 Selects the DMA transfer direction 0 DMA write receive endpoint 1 DMA read ...

Page 391: ...97 Additional Multipoint CSR Description Register Name Address Offset from 0x400430 00 Width R W Type Reset Value Description EP0_TX_FUNC_ADDR_REG 0x0080 7 RW 0 This register is used to record the address of the target function that is to be accessed through endpoint0 for transmit Required in Host mode For endpoint0 there is no companion EP0_RX_FUNC_ADDR_REG for receive EP0_TX_HUB_ADDR_REG 0x0082 ...

Page 392: ...w speed device is connected to transmit endpoint1 through a high speed USB 2 0 hub which carries out the necessary transaction translation to convert between high speed transmission and full low speed transmission In such circumstances The lower 7 bits should record the address of this USB 2 0 hub The top bit should record whether the hub has multiple transaction translators set to 0 if single tra...

Page 393: ...NC_ADDR_REG 0x0090 7 RW 0 Records the address of the target function that is to be accessed through endpoint2 for transmit Required in Host mode EP2_TX_HUB_ADDR_REG 0x0092 8 RW 0 Needs to be written where a full speed or low speed device is connected to transmit endpoint2 via a high speed USB 2 0 hub which carries out the necessary transaction translation to convert between high speed transmission...

Page 394: ...USB 2 0 hub which carries out the necessary transaction translation In such circumstances these 7 bit read write registers need to be used to record the port of that USB 2 0 hub through which the target associated with the endpoint0 is accessed This is only relevant in Host mode EP3_TX_FUNC_ADDR_REG 0x0098 7 RW 0 Records the address of the target function that is to be accessed through endpoint3 f...

Page 395: ...o convert between high speed transmission and full low speed transmission In such circumstances The lower 7 bits records the address of this USB 2 0 hub The top bit records whether the hub has multiple transaction translators set to 0 if single transaction translator set to 1 if multiple transaction translators This is relevant in Host mode only EP3_RX_HUB_PORT_REG 0x009F 7 RW 0 Needs to be writte...

Page 396: ...FUNC_ADDR_REG 0x00A4 7 RW 0 Records the address of the target function that is to be accessed through endpoint4 for receive Required in Host mode EP4_RX_HUB_ADDR_REG 0x00A6 8 RW 0 Needs to be written where a full or low speed device is connected to receive endpoint4 through a high speed USB 2 0 hub which carries out the necessary transaction translation to convert between high speed transmission a...

Page 397: ...13 4 EPx_TX_HUB_ADDR_REG Bit Definitions Notes Allowed values of x are 0 1 2 3 and 4 corresponding to endpoints 0 1 2 3 and 4 For EP1_TX_HUB_ADDR_REG register the address is 0x4004308A For EP2_TX_HUB_ADDR_REG register the address is 0x40043092 For EP3_TX_HUB_ADDR_REG register the address is 0x4004309A For EP4_TX_HUB_ADDR_REG register the address is 0x400430A2 Table 298 EPx_TX_FUNC_ADDR_REG 0x40043...

Page 398: ...ions Notes For EP1_RX_HUB_PORT_REG register the address is 0x4004308F For EP2_RX_HUB_PORT_REG register the address is 0x40043097 For EP3_RX_HUB_PORT_REG register the address is 0x4004309F For EP4_RX_HUB_PORT_REG register the address is 0x400430A7 Table 301 EPx_RX_HUB_ADDR_REG Bit Number Name Reset Value Function 7 Multiple Translators 0 Records whether the hub has multiple transaction translators ...

Page 399: ...next LPM transaction that is transmitted These values are inserted in the payload of the next LPM transaction LPM_CTRL_REG 0x40043362 Periphe ral LPM_CTRL_REG 0x40043362 Host 0x0362 8 R 0 Provides controls for LPM based on Peripheral mode and Host mode LPM_INTR_EN_REG 0x40043363 0x0363 8 R 0 Provides enable bits for the interrupts in LPM_INTR_REG If a bit in this register is set to 1 MC_NINT will ...

Page 400: ...alue Function 7 5 Reserved N A 4 LPMNAK 0 Places all endpoints in a state such that the response to all transactions other than an LPM transaction is a NAK This bit takes effect only after the USB controller has been LPM suspended In this case the USB controller continues to NAK until this bit has been cleared by software 3 2 LPMEN 0 Enables LPM in the USB controller There are three levels in whic...

Page 401: ...et Value Function 7 2 Reserved N A 1 LPMRES 0 Initiates a RESUME from the L1 state This bit differs from the classic RESUME bit POWER_REG bit2 in that the RESUME signal timing is controlled by hardware When software writes this bit resume signaling is asserted for a time specified by the HIRD field LPM_ATTR_REG bit 7 4 This bit is self clearing 0 LPMXMT 0 Transmits an LPM transaction This bit is s...

Page 402: ...N field LPM_CTRL_REG bit 3 2 is set to 11 the LPMXMT LPM_CTRL_REG bit0 is set to 1 and there is data pending in the USB controller transmit FIFOs 1 LPMNY 0 This bit is set when an LPM transaction is received and the USB controller responds with a NYET This can only occur under the following conditions The LPMEN field LPM_CTRL_REG bit 3 2 is set to 11 the LPMXMT LPM_CTRL_REG bit0 is set to 1 and th...

Page 403: ...transmitted and the device responds with a NYET 0 LPMST 0 This bit is set when an LPM transaction is transmitted and the device responds with a STALL Table 311 LPM_FADDR_REG 0x40043365 Bit Number Name Reset Value Function 7 Reserved N A 6 0 LPMFADDR 0 The LPM function address Table 310 LPM_INTR_REG 0x40043364 Host Mode continued Bit Number Name Reset Value Function ...

Page 404: ...age 2 00011 USB master weightage 3 00100 USB master weightage 4 00101 USB master weightage 5 00110 USB master weightage 6 00111 USB master weightage 7 01000 USB master weightage 8 01001 USB master weightage 9 01010 USB master weightage 10 01011 USB master weightage 11 01100 USB master weightage 12 01101 USB master weightage 13 01110 USB master weightage 14 01111 USB master weightage 15 10000 USB m...

Page 405: ... Name Address Reset Value Function 0 USB_UTMI_SEL 0x4003807C 0 This signal is used to configure USB controller interface as ULPI PHY or UTMI interface Following are the allowed values 0 ULPI PHY Interface is selected 1 UTMI Interface is selected 1 USB_DDR_SELECT 0 This signal is used to configure whether the USB controller works in Single Data Rate SDR mode or Double Data Rate DDR mode Allowed val...

Page 406: ...LID VBUSVALID and LINESTATE 1 LPI_CARKIT_EN 0 Asserted when entry is made into CarKit mode and cleared on exit from CarKit mode Table 318 EDAC_SR Bit Number Name Address Reset Value Function 10 USB_EDAC_1E 0x40038190 0 This status is updated by USB when a 1 bit SECDED error is detected and also corrected for RAM memory 11 USB_EDAC_2E 0 This status is updated by USB when a 2 bit SECDED error is det...

Page 407: ...Universal Serial Bus OTG Controller UG0331 User Guide Revision 15 0 373 ...

Page 408: ...ternal PHY support MII GMII TBI loopback support 4 KB of TX buffer and 8 KB of RX buffer Both TX and RX Buffers are protected by single error correction and dual error detection SECDED Standard Ethernet frames of 1522 bytes are supported Jumbo frames of 9000 bytes are not supported The following figure shows the details of MSS As shown TSEMAC can function as an AHB master for DMA data transfers an...

Page 409: ...2 1 EMAC Functional Blocks EMAC has five functional sub blocks AHB Engine MAC TX and RX FIFO PE MCXMAC MAC Statistics Module SGMII Module Ethernet MAC AHBEngine DMA controller AHB Master interface port DMA controller AHB Slave interface port AHB Decoder MAC TX RX FIFOs PE_MCXMAC PETMC Tx MAC Control PERMC Rx MAC Control PEHST Host Interface PETFN Transmit function PERFN Receive function PEMGT MII ...

Page 410: ...the period of pause time being requested Register definitions for the FIFO RAM access registers are intended for non real time RAM testing and system debug MAC TX and RX FIFO configuration registers one through five are intended to be written while the submodules are held in reset FIFO sizes are fixed and cannot be modified by either the MAC configuration or the firmware 11 2 1 3 PE MCXMAC The PE ...

Page 411: ...erfacing to the SGMII clock domain The SGMII core includes optional modules for 10 bit comma alignment Both transmit and receive paths leverage the physical coding sub layer and the auto negotiation sub layers of the IEEE 802 3z specification as explained in clauses 36 and 37 In the transmit direction the 10 bit encoded data is serialized and output over the interface In the receive direction the ...

Page 412: ...RX_CLK MAC_MII_FABRIC In Indicates MII management transmit clock 25 MHz for 100 Mbps mode and 2 5 MHz for 10 Mbps mode MIII_TXD MII_TX_EN MII_TX_ER signals are synchronized to MII_TX_CLK MII_MDC Out Indicates MII management data clock MII_MDO_ED Out Indicates MII management data output enable MII_MDO Out Indicates MII management data out MII_MDI In Indicates MII management data input Table 321 GMI...

Page 413: ... 9 0 MAC_TBI_FABRIC In MAC_RGGF is the 10 bit parallel receive data The receive data byte 0 containing the comma character is byte aligned to 53 125 MHz receive byte clock used to latch the bytes 0 and 2 of the receive data word TBI_TCGF 9 0 MAC_TBI_FABRIC Out MAC_TCGF is the 10 bit parallel transmit data presented in the physical layer for serialization and transmission l The order of transmissio...

Page 414: ...RDES EPCS Mode for SGMII Interface Figure 155 TBI Brought to Fabric for EPCS Soft IP for SGMII Interface SmartFusion2 MSS Ethernet MAC Mux Demux MM6 MS_MAC AHB Bus Matrix RMII RGMII RevMII SMII PHY Wrapper for GMII MII to RMII RGMII RevMII SMII MSIO FPGA Fabric SmartFusion2 MSS Ethernet MAC Mux Demux MM6 MS_MAC AHB Bus Matrix FABRIC SERDESIF0 1 EPCS SERDES SERDESIF I Os SGMI PHY GMII MII TBI ...

Page 415: ...ing a packet of up to the maximum size of packet transferred Due to a limitation in the AHB DMA controller Ethernet jumbo frames are not supported The software can either use the DMA Interrupts generated or poll semaphore bits within the descriptors to maintain synchronization with the packet streams The entry point into the buffer used at the start of any sequence of transfers is given by the des...

Page 416: ...he validity of the associated packet which is indicated by the empty flag the start address of the packet to be transmitted and its size If the empty flag is 1 then the descriptor is not associated with valid data The DMA controller termi nates the sequence of transmit packet transfers set the TxUnderrun bit in the DMA Tx Status regis ter and clear the TxEnable bit in the DMA Tx Control register T...

Page 417: ...does not currently contain any received packets 2 Bits 7 4 of the DMA Interrupt Mask register are set to specify which Rx DMA events cause a DMA interrupt to be generated 3 The location of the descriptor corresponding to the entry point in the Rx ring buffer should be written to the DMA Rx descriptor register and to enable the DMA transfer of receive packets enabled by writing a 1 the bit 0 of DMA...

Page 418: ...his interrupt Any further transfers require the DMA_RX_DESC register to be updated to record the start position in the ring buffer that is now required and the RxEnable bit is to be set to 1 again 11 5 How to Use TSEMAC TSEMAC can be configured using the Libero SoC design software Using the MSS Ethernet Configurator macro external PHY interface can be selected as shown in the following figure The ...

Page 419: ...o select the line speed for the selected interface Figure 157 Line Speed Selection in MSS EMAC Configurator Using the MSS EMAC configurator the management interface can be selected The management interface is used to exchange the control and status information with the external PHY ...

Page 420: ...Ethernet MAC UG0331 User Guide Revision 15 0 386 The following figure shows how to select the PHY management interface Figure 158 External PHY Management Interface Selections in MSS EMAC Configurator ...

Page 421: ... as TBI line speed as required Enable the management interface check box as shown in the following figure Figure 159 MSS Ethernet Configurator with TBI interface 2 Connect TBI signals to SERDES which is configured for EPCS mode as shown in the following figure Figure 160 SGMII Interface Signals TBI to SERDES ...

Page 422: ...de Revision 15 0 388 3 In design flow window of Libero SoC under compile option open Edit I O attributes option and assign pin names to PHY interface as shown in the following figure Figure 161 I O Editor With SGMII and PHY Ports ...

Page 423: ...t error or both single bit and dual bit errors can be enabled To clear these interrupts and to take necessary actions in case of dual bit error register the interrupt handler in the application code Figure 162 SECDED Configurator with Ethernet TX RAM and Ethernet RX RAM Configuration Options Microsemi provides TSEMAC firmware drivers to use with the application development The SmartFusion2 TSEMAC ...

Page 424: ...k Keil MDK and SoftConsole A sample project can be generated by right clicking the system services driver and selecting Generate sample project as shown in the following figure Figure 163 Firmware Catalog Showing the Generation of Sample Project for TSEMAC Microsemi provides the device drivers for the TSEMAC controller for SmartFusion2 device and recommends using these drivers for the application ...

Page 425: ...unction specifies the type of interface used to connect the Ethernet MAC and Ethernet PHY as well as the PHY MII management interface address It also specifies the allowed link speed and duplex mode It is at this point that the application chooses if the link speed and duplex mode will be auto negotiate with the link partner or forced to a specific speed and duplex mode Table 328 TSEMAC Firmware D...

Page 426: ...tion needs to implement a receive callback function to be notified that a packet has been received The p_user_data parameter can be optionally used to point to a memory management data structure managed by the application MSS_MAC_set_tx_callback The MSS_MAC_set_tx_callback function registers the function that will be called by the Ethernet MAC driver when a packet has been sent MSS_MAC_set_rx_call...

Page 427: ...egister Map Register Name Address Offset Register Type Reset Value Description CFG1 0x00 R W 0x80000000 MAC configuration register CFG2 0x04 R W 0x00007000 MAC configuration register IFG 0x08 R W 0x40605060 Inter packet gap and interframe gap register HALF_DUPLEX 0x0C R W 0x00A1F037 Definition of half duplex register MAX_FRAME_LENGTH 0x10 R W 0x00000600 Sets the maximum frame size in both transmit...

Page 428: ...0 Definition of A MCXFIFO configuration register 0 FIFO_CFG1 0x4C R W 0x0FFFFFFF Definition of A MCXFIFO configuration register 1 FIFO_CFG2 0x50 R W 0x1FFF1FFF Definition of A MCXFIFO configuration register 2 FIFO_CFG3 0x54 R W 0xFFF0FFF Definition of A MCXFIFO configuration register 3 FIFO_CFG4 0x58 R W 0x0 Definition of A MCXFIFO configuration register 4 FIFO_CFG5 0x5C R W 0x3FFFF Definition of ...

Page 429: ...C PE MSTAT Receive Counters Register Map Register Name Address Offset Register Type Reset Value Description RBYT 0x9C R W 0x0 The statistic counter register is incremented by the byte count of all frames received RPKT 0XA0 R W 0x0 Incremented for each frame received packet RFCS 0XA4 R W 0x0 This is incremented for each frame received that has an integral 64 to 1518 length and contains a frame chec...

Page 430: ...stem but are later dropped due to lack of system resources Table 337 EMAC PE MSTAT Transmit Counters Register Map Register Name Address Offset Register Type Reset Value Description TBYT 0XE0 R W 0x0 This is incremented for each transmitted byte including fragments of frames which are involved in collisions TPKT 0XE4 R W 0x0 This is incremented for each transmitted packet TMCA 0XE8 R W 0x0 This is ...

Page 431: ...alue CAR1 0x130 RO 0x0 This indicates the transmit and receive counters and the receive counters carry the bits The carry register bits are cleared on carry register write when the respective bit is asserted CAR2 0x134 RO 0x0 This indicates the transmit counters carry bits The carry register bits are cleared on carry register write when the respective bit is asserted CAM1 0x138 R W 0xFE01FFFF The ...

Page 432: ... address for the M SGMII is 0x1E AN NEXT PAGE TRANSMIT 0x08 RO The link partner asserts this bit to indicate additional Next Pages to follow This indicates the message page and the link partner s ability to comply with the message The PHY address for the M SGMII is 0x1E EXTENDED STATUS 0x0F RO 0xA000 This indicates that the PHY can be operated in 1000BASE X FULL DUPLEX 1000BASE X HALF DUPLEX 1000B...

Page 433: ...ame Reset Value Description 31 2 Top 30 bits of Descriptor Address 0x0 When TxEnable is set by the host the built in DMA controller reads this register to discover the location in the host memory of the first transmit packet descriptor 1 0 Ignored by the DMA controller 0x0 All descriptors are 32 bit aligned in the host memory Table 341 DMA_TX_STATUS Bit Number Name Reset Value Description 31 24 Re...

Page 434: ...ter that is incremented whenever the built in DMA controller successfully transfers a packet and is decremented whenever the host writes a 1 to bit zero of this register 16 4 Reserved 0x0 Reserved 3 BusError 0x0 When set this indicates that a host slave split retry or error response is received by the DMA controller 2 RxOverflow 0x0 Set whenever the DMA controller reads a zero empty flag in the de...

Page 435: ...e both set 5 Reserved 0x0 Reserved 4 RxPktReceived 0x0 This is set to 1 to record a RxPktReceived interrupt when the RxPktReceived bit in the DMARxStatus register and bit 4 of the DMAIntrMask register are both set 3 Bus Error 0x0 This is set to 1 to record a transmit bus error interrupt when the Bus Error bit in the DMATxStatus register and bit 3 of the DMAIntrMask register are both set 2 Reserved...

Page 436: ...rol to ignore PAUSE flow control frames 4 TRANSMIT FLOW CONTROL ENABLE 0x0 Setting this bit allows the PETMC transmit MAC Control to send PAUSE flow control frames when requested by the system Clearing this bit prevents the transmit MAC control from sending flow control frames 3 SYNCHRONIZE D RECEIVE ENABLE 0x0 This field is read only and indicates that the receive enable is synchronized to the re...

Page 437: ...CRC to all the frames Clear this bit if frames presented to the MAC have a valid length and contain a valid CRC If the PAD CRC ENABLE configuration bit or the per packet PAD CRC ENABLE is set CRC ENABLE is ignored 0 FULL DUPLEX 0x0 Setting this bit configures the PE MCXMAC to operate in Full duplex mode Clearing this bit configures the PE MCXMAC to operate in Half duplex mode only Table 349 IFG Bi...

Page 438: ...19 ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE 0x0 Setting this bit configures the Tx MAC to use the ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION setting instead of the 802 3 standard tenth collision Clearing this bit causes the Tx MAC to follow the standard binary exponential backoff rule 18 BACKPRESSURE NO BACKOFF 0x0 Setting this bit configures the Tx MAC to immediately re transmit following...

Page 439: ...t Number Name Reset Value Description 31 4 Reserved 0x0 Reserved 3 MAXIMUM FRAME LENGTH 0x0 Setting this bit causes the MAC to backoff for the maximum possible length of time This test bit is used to predict the backoff times in Half duplex mode 2 REGISTERED TRANSMIT FLOW ENABLE 0x0 Registered transmit Half duplex flow enable 1 TEST PAUSE 0x0 Setting this bit allows the MAC to be paused via the ho...

Page 440: ...causes MII Mgmt to perform Mgmt read write cycles with the 64 clocks of preamble 3 Reserved 0x0 Reserved 2 0 MGMT CLOCK SELECT 0x0 This field determines the clock frequency of the management data clock MDC MGMT Clock Select Encoding programming fields are given below Mgmt Clock Select 2 1 0 Source Clock divided by 4 0 0 0 Source Clock divided by 4 0 0 1 Source Clock divided by 6 0 1 0 Source Clock...

Page 441: ...lue Description 31 16 Reserved 0x0 Reserved 15 0 MII MGMT STATUS PHY STATUS 0x0 Following an MII Mgmt read cycle the 16 bit data can be read from this location Table 358 MII_INDICATORS Bit Number Name Reset Value Description 31 3 Reserved 0x0 Reserved 2 NOT VALID 0x0 When 1 is returned this indicates MII Mgmt Read cycle is not completed and the Read Data is not yet validated 1 SCANNING 0x0 When 1 ...

Page 442: ... MII module with the current operating speed When set 100 Mbps mode is selected When cleared 10 Mbps mode is selected 15 RESET PE100X 0x0 This bit resets the 4B 5B symbol encipher decipher logic 14 11 Reserved 0x0 Reserved 10 FORCE QUIET 0x0 When enabled the transmit data is cleared which allows the contents of the cipher to be the output When cleared the normal operation is enabled This affects t...

Page 443: ...a valid link 5 FULL DUPLEX 0x0 When read as a 1 the Serial MII PHY operates in full duplex mode When read as a 0 the Serial MII PHY operates in half duplex mode 4 SPEED 0x0 When read as a 1 the Serial MII PHY operates at 100 Mbps mode When read as a 0 the Serial MII PHY operates at 10 Mbps 3 LINK FAIL 0x0 When read as a 1 the MII Management module reads the PHY link fail register to be 1 When read...

Page 444: ...nly bit When asserted the FIFO receive interface module is enabled When de asserted the FIFO receive interface module is disabled The bit should be polled until it reaches the expected value 17 srfenrply 0x0 This is a read only bit When asserted the FIFO PE MCXMAC receive interface module is enabled When de asserted the FIFO PE MCXMAC receive interface module is disabled The bit should be polled u...

Page 445: ...n reset 1 hstrstsr 0x0 When asserted this bit places the FIFO PE MCXMAC receive interface module in reset 0 hstrstwt 0x0 When asserted this bit places the FIFO PE MCXMAC watermark module in reset Table 364 FIFO_CFG1 Bit Number Name Reset Value Description 31 28 Reserved 0x0 Reserved 27 16 cfgsrth 11 0 0xFFF This bit represents the minimum number of 4 byte locations which are simultaneously stored ...

Page 446: ...ved 0x0 Reserved 27 16 cfghwmft 0xFFF This hex value represents the maximum number of 4 byte locations which are simultaneously stored in the transmit RAM before the fthwm is asserted The fthwm is asserted whenever the amount of four byte locations used in the transmit FIFO data RAM exceeds the value programmed in the cfghwmft host register 15 12 Reserved 0x0 Reserved 11 0 cfgftth 0xFFF This bit r...

Page 447: ...ng receive statistics vector is as follows Bit Description 17 System Receive unicast Address 16 Truncated Frame 15 Receive long event 14 VLAN Tagged frame frame s length type field contained 0x8100 which is the VLAN protocol identifier 13 Frame was Unsupported Op code 12 Frame was a PAUSE control frame 11 Long event detected 10 Frame contained a dribble nibble 9 Broadcast address detected 8 Multic...

Page 448: ... Receive unicast Address 16 Truncated Frame 15 Receive long event 14 VLAN Tagged frame frame s length type field contained 0x8100 which is the VLAN protocol identifier 13 Frame was Unsupported Op code 12 Frame was a PAUSE control frame 11 Long Event detected 10 Frame contained a dribble nibble 9 Broadcast address detected 8 Multicast address detected 7 Reception OK 6 Length Type field was neither ...

Page 449: ...0x0 Reserved 12 0 hsttramradx 0x0 Host transmit RAM read address Table 372 FIFO_RAM_ACCESS3 Bit Number Name Reset Value Description 31 0 hsttramrdat 0x0 Host transmit RAM read data Table 373 FIFO_RAM_ACCESS4 Bit Number Name Reset Value Description 31 hstrramwreq 0x0 Host receive RAM write request 30 hstrramwack 0x0 Host receive RAM write acknowledge 29 24 Reserved 0x0 Reserved 23 16 hstrramwdat 39...

Page 450: ...Bit Number Name Reset Value Description 31 18 Reserved 0x0 Reserved 17 0 TR64 0x0 Transmit and receive 64 byte frame counter Incremented for each good or bad transmitted and received frame which is 64 bytes in length inclusive excluding framing bits but including FCS bytes Table 378 TR127 Bit Number Name Reset Value Description 31 18 Reserved 0x0 Reserved 17 0 TR127 0x0 Transmit and receive 65 to ...

Page 451: ...e Description 31 18 Reserved 0x0 Reserved 17 0 TRMAX 0x0 Transmit and receive 1024 to 1518 byte frame counter Incremented for each good or bad transmitted and received frame which is 1024 to 1518 bytes in length inclusive excluding framing bits but including FCS bytes Table 383 TRMGV Bit Number Name Reset Value Description 31 18 Reserved 0x0 Reserved 17 0 TRMGV 0x0 Transmit and receive 1519 to 152...

Page 452: ...or each multicast good frame of lengths smaller than 1518 non VLAN or 1522 VLAN excluding the broadcast frames This does not include range length errors Table 388 RBCA Bit Number Name Reset Value Description 31 22 Reserved 0x0 Reserved 21 0 RBCA 0x0 Receive broadcast packet counter Incremented for each Broadcast good frame of lengths smaller than 1518 non VLAN or 1522 VLAN excluding the multicast ...

Page 453: ...unter Incremented for each frame received in which the 802 3 length field does not match with the number of the data bytes actually received 46 1500 bytes The counter is not incremented if the length field is not a valid 802 3 length Table 394 RCDE Bit Number Name Reset Value Description 31 12 Reserved 0x0 Reserved 11 0 RCDE 0x0 Receive code error counter Incremented each time a valid carrier is p...

Page 454: ... Table 398 RFRG Bit Number Name Reset Value Description 31 12 Reserved 0x0 Reserved 11 0 RFRG 0x0 Receive fragments counter Incremented for each frame received which is less than 64 bytes in length and contains an invalid FCS The received frame includes integral and non integral lengths Table 399 RJBR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Reserved 11 0 Reserved 0x0 Receive jab...

Page 455: ...late collision packets all unicast broadcast and multicast packets Table 403 TMCA Bit Number Name Reset Value Description 31 18 Reserved 0x0 Reserved 17 0 TPKT 0x0 Transmit packet counter Incremented for each transmitted packet including bad packets excessive deferred packets excessive collision packets late collision packets all unicast broadcast and multicast packets Table 404 TBCA Bit Number Na...

Page 456: ...single collision packet counter Incremented for each transmitted frame which experiences exactly one collision during the transmission Table 409 TMCL Bit Number Name Reset Value Description 31 12 Reserved 0x0 Reserved 11 0 TMCL 0x0 Transmit multiple collision packet counter Incremented for each transmitted frame which experiences 2 15 collisions including any late collisions Table 410 TLCL Bit Num...

Page 457: ...Description 31 12 Reserved 0x0 Reserved 11 0 TDRP 0x0 Transmit drop frame counter Incremented each time the transmit PAUSE frame honored input to PE MSTAT is asserted Table 415 TJBR Bit Number Name Reset Value Description 31 12 Reserved 0x0 Reserved 11 0 TJBR 0x0 Transmit jabber frame counter Incremented for each oversized transmitted frame with an incorrect FCS value Table 416 TFCS Bit Number Nam...

Page 458: ... Carry register 1 TR64 counter carry bit 30 C1127 0x0 Carry register 1 TR127 counter carry bit 29 C1255 0x0 Carry register 1 TR255 counter carry bit 28 C1511 0x0 Carry register 1 TR511 counter carry bit 27 C11k 0x0 Carry register 1 TR1K counter carry bit 26 C1MAX 0x0 Carry register 1 TRMAX counter carry bit 25 C1MGV 0x0 Carry register 1 TRMGV counter carry bit 24 17 Reserved 0x0 Reserved 16 C1RBY ...

Page 459: ... TOVR counter carry bit 15 C2TUN 0x0 Carry register 2 TUND counter carry bit 14 C2TFG 0x0 Carry register 2 TFRG counter carry bit 13 C2TBY 0x0 Carry register 2 TBYT counter carry bit 12 C2TPK 0x0 Carry register 2 TPKT counter carry bit 11 C2TMC 0x0 Carry register 2 TMCA counter carry bit 10 C2TBC 0x0 Carry register 2 TBCA counter carry bit 9 C2TPF 0x0 Carry register 2 TXPF counter carry bit 8 C2TD...

Page 460: ... TRMGV counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 24 17 Reserved 0x0 Reserved 16 M1RBY 0x1 Mask register 1 RBYT counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 15 M1RPK 0x1 Mask register 1 RPKT counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 14 M1RFC 0x1 Mask register 1 RFCS counter carry bit 0 Unmask th...

Page 461: ...he counter carry bit 1 Mask the counter carry bit 1 M1RJB 0x1 Mask register 1 RJBR counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 0 M1RDR 0x1 Mask register 1 RDRP counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit Table 424 CAM2 Bit Number Name Reset Value Description 31 20 Reserved 0x0 Reserved 19 M2TJB 0x1 Mask register 2 TJBR counter car...

Page 462: ... carry bit 1 Mask the counter carry bit 7 M2TED 0x1 Mask register 2 TEDF counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 6 M2TSC 0x1 Mask register 2 TSCL counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 5 M2TMA 0x1 Mask register 2 TMCL counter carry bit 0 Unmask the counter carry bit 1 Mask the counter carry bit 4 M2TLC 0x1 Mask register 2...

Page 463: ...he PHY is capable of handling MII management frames without the 32 bit preamble field Returns 1 on read to indicate the support for suppressed preamble MII management frames 5 AUTO NEGOTIATION COMPLETE 0x0 This bit indicates that the Auto negotiation process is completed Returns 0 on read when either the auto negotiation process is underway or when the Auto negotiation function is disabled 4 REMOT...

Page 464: ... written 0000000001 for correct M SGMII operation Table 428 AN LINK PARTNER BASE PAGE ABILITY Bit Number Name Reset Value Description 15 LINK UP 0x0 When the M SGMII is integrated to a MAC such as the PE MCXMAC and is communicating with another SGMII PHY module assertion of this bit indicates that the link is up When the M SGMII is integrated to a PHY and is not integrated to MAC this bit is inval...

Page 465: ...CKNOWLEDGE 2 0x0 Used by the Next Page function to indicate that the device has the ability to comply with the message Assert this bit if the local device will comply with the message Clear the bit if the local device cannot comply with message 11 TOGGLE 0x0 This bit is read only Used to ensure synchronization with the Link Partner during Next Page exchange This bit always takes the opposite value...

Page 466: ...elds take an arbitrary value Table 432 EXTENDED STATUS Bit Number Name Reset Value Description 15 1000BASE X FULL DUPLEX 0x1 When 1 indicates that the PHY can operate in 1000BASE X Full duplex mode When 0 indicates that the PHY cannot operate in 1000BASE X Full duplex mode 14 1000BASE X HALF DUPLEX 0x0 When 1 indicates that the PHY can operate in 1000BASE X Half duplex mode When 0 indicates that t...

Page 467: ... 11 10 Reserved 0x0 Reserved 9 0 CUSTOM JITTER PATTERN 0x0 Used in conjunction with JITTER PATTERN SELECT and JITTER DIAGNOSTIC ENABLE Set this field to the desired custom pattern which is transmitted continuously Table 434 TBI CONTROL Bit Number Name Reset Value Description 15 SOFT RESET 0x0 This bit resets the functional modules in the M SGMII Clear it for normal operation Its default is 0 14 SH...

Page 468: ...and status register access Supports UCAD MCAD and broadcast type of packets Supports hash based address filtering for UCAD and MCAD packets Provides mechanism to the upper layer to reject or accept the frames 8 AUTO NEGOTIATION SENSE 0x0 Set this bit to allow the auto negotiation for 1000BASE X which is used to exchange information between link partners Clear this bit when IEEE 802 3z Clause 37 be...

Page 469: ...I Ethernet PHY The following figure shows CoreMACFilter interaction with MSS MAC and SGMII Ethernet PHY Figure 165 CoreMACFilter interaction with MSS MAC and SGMII Ethernet PHY For more information on CoreMACFilter refer to CoreMACFilter handbook 6PDUW XVLRQ 066 0 0 7 DWD DVH 7 0 WKHUQHW 3 RUH0 LOWHU 0 5 DWD 5 B 55 6PDUW XVLRQ 066 0 7 7 DWD 7 5 DWD 6 5 6 5 DWD DVH 7 6 0 WKHUQHW 3 6 5 6 RUH0 LOWHU ...

Page 470: ... CAN controller is shown in the following figure Transmit and receive message buffers are single error corrected double error detected SECDED through the error detection and correction EDAC controller The functional behavior of the CAN instance must be defined at the application level using the SmartFusion2 MSS CAN firmware driver provided by Microsemi Refer to the CAN Firmware Driver User Guide f...

Page 471: ...ontrol The CAN controller can be enabled or disabled using the MSS configurator in Libero SoC depending on the application needs When it is disabled the CAN controller is held in reset lowest power state Refer to the Hardware Design Flow page 446 for more information on how to enable or disable the CAN controller using Libero SoC 12 1 6 System Dependencies 12 1 6 1 Reset The CAN controller resets ...

Page 472: ...ation is selected using the configuration register Following are the arbitration types Round Robin Buffers are served in a defined order 0 1 2 31 0 1 A particular buffer is only selected if its TxReq flag is set This scheme guarantees that all buffers receive the same probability to send a message Fixed Priority Buffer 0 has the highest priority This way it is possible to designate buffer 0 as the...

Page 473: ... TxReq and TxAbort flags are cleared when the message is removed or when the message wins arbitration At the same time the sst_failure interrupt is asserted 12 2 3 Receive Procedures The CAN controller provides 32 individual receive message buffers Each one has its own message filter mask Automatic reply to RTR messages is supported If a message is accepted in a receive buffer its MsgAv flag is se...

Page 474: ...the incoming bit is a don t care 12 2 3 2 1 RTR Auto Reply The CAN controller supports automatic answering of RTR message requests All 32 receive buffers support this feature If an RTR message is accepted in a receive buffer where the RTRreply flag is set then this buffer automatically replies to this message with the content of this receive buffer The RTRreply pending flag is set when the RTR mes...

Page 475: ...TATUS 10 INT_STATUS 11 INT_STATUS 13 INT_STATUS 12 INT_STATUS 14 INT_STATUS 15 INT_ENABLE 2 INT_ENABLE 4 INT_ENABLE 3 INT_ENABLE 5 INT_ENABLE 6 INT_ENABLE 7 INT_ENABLE 9 INT_ENABLE 10 INT_ENABLE 11 INT_ENABLE 12 INT_ENABLE 14 INT_ENABLE 15 INT_ENABLE 13 INT_ENABLE 8 RxIntEbI RX_MSG0 MsgAv RX_MSG0 RxIntEbI RX_MSG31 MsgAv RX_MSG31 INT_ENABLE 12 INT_ENABLE 11 TxIntEbI TX_MSG31 TxIntEbI TX_MSG0 TxReq ...

Page 476: ...ct to the MSS GPIOs Connecting the CAN ports to the allocated CAN MSIOs or fabric or both is done in the CAN Configurator The Advanced Options in the Configuration window provide the options to enable extra connectivity between the MSIOs and fabric or GPIOs or both fabric and GPIOs as shown in the following figure Figure 170 CAN Configurator GUI Table 436 Test Modes Loop back Listen only Comment 0...

Page 477: ...for the CAN peripheral The following table summarizes the valid connections for different configurations that are available in the CAN configurator dialog Each port is connected to the allocated CAN MSIO or to the fabric through the Main Connection drop down menu as shown in the following figure Figure 171 Main Connection Options Either MSIO or Fabric Table 437 Summary of Different Valid CAN Conne...

Page 478: ...or more information refer to the MSS CAN Configurator User Guide The functional behavior of the CAN instance must be defined at the application level using the SmartFusion2 MSS CAN firmware driver provided by Microsemi Refer to the CAN Firmware Driver User Guide for more details 12 3 2 EDAC CAN Configuration In radiation prone environments storage elements such as RAMs and FIFOs are susceptible to...

Page 479: ... can be used by the design Enable EDAC Use to enable EDAC functionality for the CAN controller Enable EDAC Interrupt s Use to enable the EDAC interrupts for the CAN controller Interrupts for 1 bit error and 2 bit error or both can be enabled as shown in the preceding figure Refer to the MSS EDAC Configuration User Guide for more information on the SECDED configurator options and ports descriptions...

Page 480: ... as shown in the following figure Figure 174 Enabling CAN Controller With MSS Configurator When the CAN is enabled CAN_RX CAN_TX and CAN_TX_EN_N will be promoted to the top MSS component as shown in the following figure Figure 175 CAN Signals Generate the component by clicking Generate Component or by selecting Generate Component from the SmartDesign menu The firmware driver folder and the SoftCon...

Page 481: ...mware Project The SoftConsole folder contains the required mss_driver which provides a set of functions for controlling the MSS CAN peripheral Note If the drivers are not generated make sure that the CAN firmware driver downloaded into the vault from the repositories is available and Generate option is enabled in the DesignFirmware window as shown in the following figure Figure 176 Firmware Driver...

Page 482: ...ection Flow Chart 12 5 2 Use Case 2 SRAM Test Mode In addition to the test modes described in the Test Modes section the CAN controller can be put into SRAM test mode The CAN controller has a built in RAM which is protected by EDAC that is used to store the Receive and Transmit messages To support software based memory testing the CAN controller can be put into SRAM test mode When this SRAM test m...

Page 483: ...SRAM addresses Table 438 APB to SRAM Address Mapping APB Address SRAM Address Description 0x020 0x000 TxObject0 Control Bits 0x024 0x001 TxObject0 Identifier Bits 0x028 0x002 TxObject0 Data High Bits 0x02C 0x003 TxObject0 Data Low Bits 0x030 0x03C 0x004 0x007 TxObject1 0x040 0x04C 0x008 0x00B TxObject2 0x050 0x05C 0x00C 0x00F TxObject3 0x060 0x06C 0x010 0x013 TxObject4 0x070 0x07C 0x014 0x017 TxOb...

Page 484: ...ive Message Object 6 0x300 0x31C 0x0B8 0x0BF Receive Message Object 7 0x320 0x33C 0x0C0 0x0C7 Receive Message Object 8 0x340 0x35C 0x0C8 0x0CF Receive Message Object 9 0x360 0x37C 0x0D0 0x0D7 Receive Message Object 10 0x380 0x39C 0x0D8 0x0DF Receive Message Object 11 0x3A0 0x3BC 0x0E0 0x0E7 Receive Message Object 12 0x3C0 0x3DC 0x0E8 0x0EF Receive Message Object 13 0x3E0 0x3FC 0x0F0 0x0F7 Receive ...

Page 485: ...tion EDAC_CR 0x38 RW P Register SYSRESET_N Configures EDAC component of the CAN To enable or disable the EDAC for the CAN set the CAN_EDAC_EN bit 6th bit in this register as follows 0 EDAC is disabled 1 EDAC is enabled EDAC_IRQ_ENABLE_CR 0x78 RW P Register SYSRESET_N Configures EDAC interrupts To set 1 bit error or 2 bit error set the CAN_EDAC_1E_EN and CAN_EDAC_2E_N bits the 12th and 13th bits in...

Page 486: ...in Table 441 page 452 CLR_EDAC_COUNTERS 0x1A4 W1P SYSRESET_N Clear EDAC counters This is a pulse generated to clear the 16 bit counter value in CAN corresponding to the count value of EDAC 1 bit or 2 bit errors This in turn clears the upper 16 bits of CAN_EDAC_CNT register Table 440 CAN Controller Soft Reset Bit in the SOFT_RESET_CR Register Bit Number Name R W Reset Value Description 13 CAN_SOFTR...

Page 487: ... RX_MSG0_DATA_HIGH 0x228 R W 0 Receive Message0 buffer data high register RX_MSG0_DATA_LOW 0x22C R W 0 Receive Message0 buffer data low register RX_MSG0_AMR 0x230 R W 0 Acceptance mask register AMR The AMR register defines whether the incoming bit is checked against the ACR register RX_MSG0_ACR 0x234 R W 0 Acceptance code register ACR RX_MSG0_AMR_DATA 0x238 R W 0 AMR Data RX_MSG0_ACR_DATA 0x23C R ...

Page 488: ...capture mode 0 Free running The ECR register shows the current bit position within the CAN frame 1 Capture mode The ECR register shows the bit position and type of the last captured CAN error 13 SWAP_ENDIAN The byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol 0 CAN data byte position is not swapped big e...

Page 489: ...Function 31 16 Revision_Control This field contains the version of the CAN core in the following format This is a read only field major version minor version revision number 31 28 Major version 27 24 Minor version 23 16 Revision number 15 4 Reserved 0 Reserved 3 0 CAN_COMMAND 3 0 SRAM Test mode 0 Normal operation 1 Enable SRAM Test mode CAN_COMMAND 2 0 Loopback test mode 0 Normal operation 1 Loopb...

Page 490: ...y having to set the TxReq and TxAbort flags without taking care of the special flags 22 Reserved 0 Reserved 21 RTR 0 RTR control flag bit 0 Standard message 1 RTR message 20 IDE 0 Extended identifier bit Control flag bit 0 This is a standard format message 1 This is an extended format message 19 16 DLC 0 Data length code Control flag bit Invalid values are transmitted as they are but the number of...

Page 491: ...e 1 23 16 CAN data byte 2 15 8 CAN data byte 3 7 0 CAN data byte 4 The byte mapping can be set using the CAN swap_endian configuration bit swap_endian 0 default 31 24 CAN data byte 1 23 16 CAN data byte 2 15 8 CAN data byte 3 7 0 CAN data byte 4 swap_endian 1 31 24 CAN data byte 4 23 16 CAN data byte 3 15 8 CAN data byte 2 7 0 CAN data byte 1 Table 447 TX_MSG0_DATA_LOW Bit Number Name Reset Value ...

Page 492: ...ssage12 buffer registers TX_MSG13 Buffer 0x0F0 0x0FC R W 0 Transmit Message13 buffer registers TX_MSG14 Buffer 0x100 0X10C R W 0 Transmit Message14 buffer registers TX_MSG15 Buffer 0x110 0X11C R W 0 Transmit Message15 buffer registers TX_MSG16 Buffer 0x120 0X12C R W 0 Transmit Message16 buffer registers TX_MSG17 Buffer 0x130 0X13C R W 0 Transmit Message17 buffer registers TX_MSG18 Buffer 0x140 0X1...

Page 493: ...available in TxMessage buffer 21 20 TxMessage20 0 Message available in TxMessage buffer 20 19 TxMessage19 0 Message available in TxMessage buffer 19 18 TxMessage18 0 Message available in TxMessage buffer 18 17 TxMessage17 0 Message available in TxMessage buffer 17 16 TxMessage16 0 Message available in TxMessage buffer 16 15 TxMessage15 0 Message available in TxMessage buffer 15 14 TxMessage14 0 Me...

Page 494: ...a regular message 1 This is an RTR message 20 IDE 0 Extended identifier bit Control bit 0 This is a standard format message 1 This is an extended format message 19 16 DLC 0 Data length code Control bits 0 Message has 0 data byte 1 Message has 1 data byte 8 Message has 8 data bytes 9 15 Message has 8 data bytes 15 8 Reserved 0 Reserved 7 WPNL 1 Write protect not low 0 Bits 6 3 remain unchanged 1 Th...

Page 495: ...ledges receipt of new message or transmission of RTR auto reply message Before acknowledging receipt of a new message the message content must be copied into system memory Acknowledging a message clears the MsgAv flag Table 451 RX_MSG0_ID Bit Number Name Reset Value Description 31 3 ID 28 0 RxMessage0 buffer identifier 29 bit wide 2 0 Reserved 0 N A Table 452 RX_MSG0_DATA_HIGH Bit Number Name Rese...

Page 496: ...on 31 0 RX_MSG0_AMR Receive Message0 buffer AMR bits 31 3 Identifier 2 IDE 1 RTR 0 Reserved AMR 0 The incoming bit is checked against the respective ACR The message is not accepted when the incoming bit does not match with the respective ACR flag 1 The incoming bit is a don t care Table 455 RX_MSG0_ACR Bit Number Name Reset Value Description 31 0 RX_MSG0_ACR Receive Message0 buffer ACR bits 31 3 I...

Page 497: ...ceive Message11 buffer registers RX_MSG12 Buffer 0x3A0 0x3BC R W 0 Receive Message12 buffer registers RX_MSG13 Buffer 0x3C0 0x3DC R W 0 Receive Message13 buffer registers RX_MSG14 Buffer 0x3E0 0x3FC R W 0 Receive Message14 buffer registers RX_MSG15 Buffer 0x400 0x41C R W 0 Receive Message15 buffer registers RX_MSG16 Buffer 0x420 0x43C R W 0 Receive Message16 buffer registers RX_MSG17 Buffer 0x440 ...

Page 498: ...ailable in RxMessage buffer 21 20 RxMessage20 0 Message available in RxMessage buffer 20 19 RxMessage19 0 Message available in RxMessage buffer 19 18 RxMessage18 0 Message available in RxMessage buffer 18 17 RxMessage17 0 Message available in RxMessage buffer 17 16 RxMessage16 0 Message available in RxMessage buffer 16 15 RxMessage15 0 Message available in RxMessage buffer 15 14 RxMessage14 0 Mess...

Page 499: ...eeds to be set again The following table provides the bits descriptions in the ECR register Table 460 ECR Bit Number Name Reset Value Description 31 17 Reserved 0 Reserved 16 12 Field 0 This specifies the field of the ECR 0x00 Stopped 0x01 Synchronize 0x05 Interframe 0x06 Bus idle 0x07 Start of frame 0x08 Arbitration 0x09 Control 0x0A Data 0x0B CRC 0x0C ACK 0x0D End of frame 0x10 Error flag 0x11 E...

Page 500: ...61 ERROR_STATUS Bit Number Name Reset Value Description 31 20 Reserved 0 Reserved 19 rxgte96 0 The receive error counter is greater than or equal to 96 dec 18 txgte96 0 The transmit error counter is greater than or equal to 96 dec 17 16 error_state 1 0 0 The error state of the CAN mode 00 error active normal operation 01 error passive 1x bus off 15 8 rx_err_cnt 7 0 0 The receive error counter as d...

Page 501: ...RE 0 Single shot transmission failure 0 Normal operation 1 A buffer set for single shot transmission experienced an arbitration loss or a bus error during transmission 14 STUCK_AT_0 0 Stuck at dominant error 0 Normal operation 1 Indicates if receive RX input remains stuck at 0 dominant level for more than 11 consecutive bit times 13 RTR_MSG 0 RTR auto reply message sent 0 Normal operation 1 Indica...

Page 502: ... Bit stuffing error 0 Normal operation 1 Indicates that a CAN bit stuffing error is detected 4 BIT_ERR 0 Bit error 0 Normal operation 1 Indicates that a CAN bit error is detected 3 OVR_LOAD 0 Overload message detected 0 Normal operation 1 Indicates that a CAN overload message is detected 2 ARB_LOSS 0 Arbitration loss 0 Normal operation 1 The message arbitration was lost while sending a message The...

Page 503: ...onous and synchronous operations Full programmable serial interface characteristics Data width is programmable to 5 6 7 or 8 bits Even odd or no parity bit generation detection 1 1 and 2 stop bit generation 9 bit address flag capability used for multi drop addressing topologies Separate transmit Tx and receive Rx FIFOs to reduce processor interrupt service loading Single wire half duplex mode in w...

Page 504: ...put data into parallel form to facilitate reading by the Cortex M3 processor The baud rate generator contains free running counters and utilizes the asynchronous and synchronous baud rate generation circuits The input filters in MMUART suppress the noise and spikes of incoming clock signals and serial input data based on the filter length The RZI modulation demodulation blocks are intended to allo...

Page 505: ...nformation to the Cortex M3 processor through the MSR This register also indicates that the DSRn signal is changed since the register was read last time This signal can either go to the fabric or to the I O pad MMUART_X_DCD Input Low Data carrier detect This signal is used in the modem interface The active Low signal is an input that indicates when the attached device modem has detected a carrier ...

Page 506: ...pin This signal can either go to the fabric or to the I O pad MMUART_X_TXD Output Serial output data This is the data transmitted from MMUART It is synchronized with the BAUDOUT output pin This signal can either go to the fabric or to the I O pad MMUART_X_SCK_IN Input Serial input synchronous clock The MMUART_X_SCK can be configured as an input synchronous clock from master when the MMUART_X acts ...

Page 507: ...M0 and Receiver Timeout Register RTO Table 490 page 503 10 Set transmit time guard by using Transmitter Time Guard Register TTG Table 489 page 503 11 Set input filter length to suppress spikes by using Glitch Filter Register GFR Table Table 488 page 502 12 Configure the baud rate of MMUART by using Baud Rate Registers DLR DMR and DFR 13 Set the word length stop bits and parity of MMUART by using L...

Page 508: ...each MMUART peripheral The MMUART_0_INT signal is generated by MMUART_0 and is mapped to INTISR 10 in the Cortex M3 processor nested vectored interrupt controller NVIC The MMUART_1_INT signal is generated by MMUART_1 and is mapped to INTISR 11 in the Cortex M3 processor NVIC Both interrupt enable bits within NVIC INTISR 10 and INTISR 11 correspond to bit locations 10 and 11 MMUART interrupts can b...

Page 509: ...e based on the baud rate registers MMUART may receive and transmit data based on this clock full duplex Software may drive half duplex communication based on the application and a single line may be used for MMUART_X_TXD and MMUART_X_RXD transmissions through a bi directional pad While transmitting data the reception is inhibited and vice versa This can be done by enabling the single wire half dup...

Page 510: ...ollowing equation is used to calculate the fractional baud rate where APB_X_CLK Input reference clock APB_0_CLK for MMUART_0 and APB_1_CLK for MMUART_1 DMR Divisor latch for MSB DLR Divisor latch for LSB DFR Fractional divisor register If a baud rate value of 1 and 1 64th 1 015625 is required set the DLR to 1 the DMR to 0 and DFR to 1 Following examples illustrate the use of fractional baud rate R...

Page 511: ...ous Slave mode the MMUART accepts an input clock that is synchronized to the data The asynchronous state machine is harnessed to self synchronize the start bit to a clock edge With this circuit the input clock can be Bit Rate Modulation with Tbit Times BR 4 64 CCC per count BR 5 16x5 80 CCC per count Integer 1 Tbit Integer Tbit Integer Tbit Fractional Tbit 4 and 32 64 th 4 5 Shown is Tbit modulati...

Page 512: ...transmitter blocks use an internally generated synchronous clock which must be no greater than APB clock frequency The output clock MMUART_X_SCK_OUT is provided to the slave devices The internally generated synchronous clock is set with the same baud rate divisor registers that are used in the Asynchronous mode The Fractional baud rate generation mode should not be used in the Synchronous mode as ...

Page 513: ... flip flops are used Setting the GLR value to 1 adds a metastability flip flop and provides no spike filtering GLR values 2 to 7 further filter the spikes in the output received from flip flops Thus this method helps to suppress spikes for GLR width greater than 1 APB clock cycle An example is shown in the following figure with GLR 4 In all cases positive edge and negative edge signals are generat...

Page 514: ... field followed by a protected identifier field PID Figure 187 LIN Header 13 2 4 3 1 Break Sync Detection When the LIN header detection block is enabled with the ELIN bit MM0 the LIN circuit automatically detects break fields greater than 11 Tbits bit time of the currently running baud rate The LIN circuit calculates the number of APB clock cycles from the 1st sync byte falling edge to the fifth a...

Page 515: ...n the header This field provides identification for each message on the network and ultimately determines which nodes in the network receive or respond to each transmission All slave tasks continually listen for PID fields verify their parities and determine if they have to receive data or send data for this particular identifier The LINSI interrupt resets the FIFO address pointers so that the PID...

Page 516: ...dulator in the TxD and RxD signal paths Figure 191 RZI Modulation RZI demodulation takes pulses that are 3 16th of a baud rate clock long and transforms it to the standard non return to zero NRZ UART signal which is then fed into the main UART Rx blocks Similarly RZI modulation takes the outgoing UART NRZ Tx signal and creates 3 16th pulses out 13 2 4 4 1 RZI to NRZ Demodulation The RZI to NRZ dem...

Page 517: ...hes zero and the NRZ signal is still Low another output pulse is generated otherwise no pulse is generated The output of the modulator can be an inverted version of the following figure with the EITX configuration bit in the MM1 Additionally the output can be 1 4 widths instead of 3 16th using the EITP bit Also the EIRD enable bit RZI mod demod bit in MM1 has to be enabled The following example sh...

Page 518: ...the address flag If an address flag is received and the associated 8 bit data matches the address in the ADR register the Rx FIFO is enabled In this mode the software does not check the address and only receives Rx data once the address is matched Disabling the Rx FIFO occurs either by address flag being re sent with a non matching address value automatic or the EAFC bit in MM2 is set An example f...

Page 519: ...guard time which is composed of 2 bit times The transmitter shifts all the data out except during the guard time The guard time is used by the receiver to NACK the transmission When the EERR bit in MM2 is set the receiver will force an error signal to transmit out if an incoming parity error is detected In this case the I O signal is held Low for one Tbit time starting from 10 5 When transmitting ...

Page 520: ...lication by using Libero SoC 1 Enable MMUART_0 and or MMUART_1 instance by using the MSS configurator in the application as shown in the following figure Figure 198 Enable MMUART 2 Stops Bits Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit ACK NACK 2 1 0 12 11 10 5 10 9 8 7 6 5 4 3 2 1 0 Parity Rx Data TE Tx sout Parity Error NACK Transmit Enable Output enabled during Rx ACK ...

Page 521: ... the following figure Use the Main Connection drop down list to connect the ports of enabled MMUART_0 instance to an I O Click the highlighted Users Guide button to find more information on MMUART configuration details Figure 199 MSS MMUART Configurator 3 The MMUART_0 interface signals in the MSS component are shown in the following figure Figure 200 MMUART Interface Signals ...

Page 522: ...semi Firmware Catalog The following table lists main APIs for MMUART For complete information on the APIs refer to the SmartFusion2 MSS UART Driver User Guide as shown in the preceding figure Table 466 MSS MMUART APIs Category API Description Initialization and configuration functions MSS_UART_init Initializes and configures the MMUART MSS_UART_lin_init Initializes and configures the MMUART for LI...

Page 523: ...mulation User Guide for more information 13 3 2 MMUART Use Models 13 3 2 1 Use Model Communicating with Host PC through MMUART Peripheral Interface This use model explains the configuration of MSS MMUART to communicate with the Host PC Hyper Terminal program Figure 203 Setup to Communicate With Host PC Through MMUART Interface Block Diagram Follow Design Flow page 486 to configure MMUART_0 in the ...

Page 524: ...e control and status registers for MMUART _0 and MMUART_1 Table 467 MMUART Register Definitions Register Name Divisor Latch Access Bit DLAB 1 1 DLAB is the MSB of the line control register LCR bit 7 Addres s Offset Read Write Reset Value Description RBR 0 0x0 R N A Receiver buffer register THR 0 0x0 W N A Transmit holding register DLR 1 0x0 R W 0x01 Divisor latch LSB DMR 1 0x04 R W 0 Divisor latch...

Page 525: ...e data bits to be transmitted Bit 0 is the LSB and is transmitted first The MSB may be transmitted first if it is configured with the E_MSB_TX bit in the MM1 The reset value is unknown since the register is loaded with data in the transmit FIFO The DLAB bit 7 of LCR must be 0 to write to this register This register is write only Reading from this register with the DLAB 0 reads the RBR register val...

Page 526: ...not used If input filtering is used then the maximum input clock frequency is determined by the following equation The glitch filter length GLR can be configured by setting the bits in glitch filter register GFR 13 4 4 2 Fractional Baud Rate Register The baud rate divisor value is a 22 bit number consisting of a 16 bit integer and a 6 bit fractional part This is used by the baud rate generator to ...

Page 527: ...rence clock is 18 432 MHz FAPBCLK 18 432 MHz Fractional BR 134 5 Hence calculate the divisor value 18 432 106 16 134 5 8 565 05 The integer part of divisor 8565 and fractional part of divisor 0 05 Therefore the fractional part k integer 0 05 64 0 5 3 7 4 Table 471 DLR Bit Number Name R W Reset Value Description 7 0 DLR R W 0x01 This divisor latch LSB register DLR holds the LSB of the integer divis...

Page 528: ... 4 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 EDSSI R W 0 Modem status interrupt enable 0 Disabled default 1 Enabled 2 ELSI R W 0 Receiver line status interrupt enable 0 Disabled default 1 Enabled 1 ETBEI R W 0 Transmitter holding register...

Page 529: ...available interrupt modem status interrupt Reading the receiver buffer register RBR or the FIFO drops below the trigger level resets this interrupt 0b1100 Second priority Character timeout indication interrupt occurs when no characters have been read from the Rx FIFO during the last four character times and there was at least one character in it during this time Reading the RBR resets this interru...

Page 530: ...lue of a reserved bit should be preserved across a read modify write operation 4 LINSI Clean on R 0 LIN sync detection interrupt ID This bit set when 5th falling edge is detected by the sync timer It resets the FIFO address pointers so that the PID will be in the first location Reading the IIM register clears this interrupt 3 LINBI Clean on R 0 LIN break interrupt set automatically when break leng...

Page 531: ...p bits is 2 for all other cases not described above STB 1 and WLS 01 10 or 11 1 0 WLS R W 0 Word length select 0b00 5 bits default 0b01 6 bits 0b10 7 bits 0b11 8 bits Table 481 MCR Bit Number Name R W Reset Value Description 7 Reserved R W 0 The software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved acro...

Page 532: ...gnal Active Low 0 RTSn is set to 1 default 1 RTSn is set to 0 0 DTR R W 0 Data terminal ready MMUART_x_DTR output Active Low 0 DTRn output is set to 1 default 1 DTRn output is set to 0 Table 482 LSR Bit Number Name R W Reset Value Description 7 FIER R 0 This bit is set when there is at least one parity error framing error or break indication in the FIFO FIER is cleared when Cortex M3 processor rea...

Page 533: ... register The character in the shift register is overwritten but it is not transferred to the FIFO 0 DR R 0 Data ready DR Indicates when a data byte is received and stored in the receive buffer or the FIFO DR is cleared to 0 when the Cortex M3 processor reads the data from the receive buffer or the FIFO Table 483 MSR Bit Number Name R W Reset Value Description 7 DCD R 0 Data carrier detect DCD MMU...

Page 534: ...eiver timeout RTO Writing this bit enables the timeout and restarts the counter value The timeout value is determined by the RTO register 0 Disabled default 1 Enabled 5 ETTG R W 0 Enable transmitter time guard TTG The time guard value is determined by the TTG Register 0 Disabled default 1 Enabled 4 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with...

Page 535: ...d 1 E_MSB_TX R W 0 LSB or MSB can be sent first by configuring this bit By default the THR bit 0 is the LSB and is the first transmitted bit Bit 0 of the THR may be configured as the last transmitted bit MSB 0 THR s bit 0 is the first transmitted bit LSB default 1 THR s bit 0 is the last transmitted bit MSB 0 E_MSB_RX R W 0 LSB or MSB can be received first by configuring this bit By default the re...

Page 536: ...eserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 0 GLR R W 0 The glitch filter resynchronizes GLR and suppresses random input noise from MMUART_x_RXD serial input data and MMUART_x_SCK_IN serial input clock in synchronous mode based on the filter lengt...

Page 537: ...gister sets the counter value and enables if the ERTO bit in the MM0 is enabled You can configure the timeout value by writing into this register The RTO counts when the Rx block input state is idle is reset when a start condition occurs and restarts counting upon returning to the idle state When the RTO value is reached the RTOII interrupt is set Re writing the RTO register clears the interrupt a...

Page 538: ...rable slave select operation Configurable clock polarity Separate transmit Tx and receive Rx FIFOs to reduce interrupt service loading Processor controlled and PDMA controlled mode of data transfer The following figure shows details of the microcontroller subsystem MSS The SPI peripherals are interfaced to the AHB bus matrix through the APB interfaces APB_0 and APB_1 Figure 204 Microcontroller Sub...

Page 539: ...s SPI _0 on the APB_0 bus or SPI_1 on the APB_1 bus 14 2 1 1 Transmit and Receive FIFOs The SPI controller embeds two 4 32 depth width FIFOs for receive and transmit as shown in Figure 205 page 505 These FIFOs are accessible through RX data and TX data registers refer to the SPI Register Details page 528 Writing to the TX data register causes the data to be written to the transmit FIFO This is emp...

Page 540: ...ollowing table lists the SPI signals 14 2 2 2 Data Transfer Protocol Details The SmartFusion2 SPI controller supports the following data transfer protocols Motorola SPI Protocol National Semiconductor MICROWIRE Protocol Texas Instruments Synchronous Serial Protocol Slave Protocol Engine This section describes the data transfer protocols timing diagrams signal requirements and error case scenarios ...

Page 541: ...PI_CLK is driven to Low Figure 207 page 508 When SPO is High and no data is transferred SPI_CLK is driven to High Figure 209 page 509 The following table summarizes the clock active edges in various SPI master modes Table 493 Data Transfer Modes Data Transfer Mode SPO SPH Mode 0 0 0 Mode 1 0 1 Mode 2 1 0 Mode 3 1 1 Table 494 Summary of Master SPI Modes Mode SPS SPO SPH Clock in Idle Sample Edge Sh...

Page 542: ...nd deasserted at the end of the transfer after the last frame is sent National Semiconductor Microwire 0 0 0 Low Rising Falling High Normal operation SPI_X_CLK only generated with select and data bits 1 Low Rising Falling High Forces IDLE cycles SPI_X_SS 0 deactivated between back to back frames 1 Running Rising Falling High SPI_X_CLK is free running 1 Low Rising Falling High After sending the com...

Page 543: ... transmit when the data is available setup time The output signal is held on long enough for the recipient to sample the data hold time The minimum setup and hold time is one half SPI_X_CLK In slave mode the input clock is withdrawn at the end of the transfer For example consider the waveform for Single Frame Transfer Mode 2 SPO 1 SPH 0 In this case data is sampled on the falling edge of the clock...

Page 544: ...line of the interfaces to the required flash EEPROM devices that shows how they can be driven using Motorola SPI modes In each of these modes the SPI controller is configured as a master with the slave select line connected to the chip select of the memory device Devices Requiring Data Frame Sizes of Up to 32 Bits Serial flash EEPROM devices such as the Atmel 25010 020 040 have a data frame size s...

Page 545: ...ration for Atmel 25010 020 040 Devices The following figure shows the read operation timing for Atmel 25010 020 040 devices For the read operation the data frame size is set to 24 bits and the SPI controller is configured with SPO 0 SPH 0 On completing the least significant byte of the received data frame corresponds to the data read Figure 212 Read Operation Timing Note The first byte contains th...

Page 546: ... following The Tx and Rx done interrupts Terminates the auto fill operation In slave operation it is possible for TXRXDFCOUNT to miscount actual transmitted and received frames if the transmit FIFO under run condition occurs If this is likely in an application Microsemi recommends that TXRXDFCOUNT not be used and that it be disabled Instead use the CMDINT and SSEND bits in the raw interrupt status...

Page 547: ...O transmit word is the control byte The total data frame size supplied must be at least 12 bits long 8 bits for the control word and a minimum of 4 bits for data payload Only the output data is sampled and inserted in the receive FIFO Figure 214 National Semiconductor MICROWAVE Single Frame Transfer 14 2 2 4 2 Multiple Frame Transfer In the multiple frame transfer shown in the following figure the...

Page 548: ...s multiple frame transfer Figure 216 TI Synchronous Serial Single Frame Transfer Figure 217 TI Synchronous Serial Multiple Frame Transfer 14 2 2 5 1 TI Synchronous Serial Error Case Scenarios When the SPI controller is configured for the TI synchronous serial protocol while in slave mode it responds to failure events These failure events on slave select SPI_X_SS x and the slave clock SPI_X_CLK are...

Page 549: ...o the SPI peripheral as the slave Data bytes are optional Figure 218 SPE Command Data Format The first receive byte of the sequence after SPI_X_SS x asserts is always a command byte The slave always responds with a status byte which is the contents of the HWSTATUS register Note Set two bits in the HWSTATUS register to facilitate additional handshaking schemes between SPI master and SPI slave 14 2 ...

Page 550: ... This is repeated until the slave indicates it is ready and can accept any associated command data no RxBUSY 3 The master sends a read command and any associated data bytes for example a read address On receiving the sequence the slave stores the command byte and data in the receive FIFO User logic examines the command and data bytes and puts the requested data in the transmit FIFO As soon as it h...

Page 551: ... from the main MSS clock M3_CLK Each APB clock can be programmed individually as M3_CLK is divided by 1 2 4 or 8 Refer to the UG0449 SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information The SPI clocks in master mode are derived from APB_0_CLK APB_1_CLK Master mode and slave mode SPI data rates depend on the APB clock as given below Master mode SPI data rate Programmable from ...

Page 552: ...fers are autonomously controlled by the PDMA engine 14 2 4 2 1 Processor Controlled Mode In this mode the size of the data frames set in register TXRXDF_SIZE and their numbers set in the CONTROL TXRXDFCOUNT field are specified The data frame size specifies the number of bits being shifted out or being received per frame On completing each transfer after a specified number of data frames 1 by defau...

Page 553: ...es before the transmission begins 14 2 4 4 1 RX Overflow An Rx overflow condition arises when the receive FIFO has not been emptied in time As a result the last write to the receive FIFO from the channel overwrites the data that is received earlier and which is not read by the host processor Eventually the FIFO fills up and subsequent writes by the channel cause the Rx to overflow The corrective a...

Page 554: ...vision 15 0 520 14 3 1 Design Flow The following steps are used to enable the SPI in the application by using Libero SoC 1 Enable SPI_0 and or SPI_1 instance by using the MSS configurator in the application as shown in the following figure Figure 219 Enable SPI ...

Page 555: ...number of Slaves to 1 and the ports of enabled SPI_0 instance to an IO or Fabric by using MSS SPI_0 Configurator as shown in the following figures Click the highlighted Users Guide button to find more information on SPI configuration details Figure 220 MSS SPI Configurator Connection Type IO ...

Page 556: ...roller UG0331 User Guide Revision 15 0 522 Figure 221 MSS SPI Configurator Connection Type Fabric 3 The SPI_0 interface signals in the MSS component are shown in the following figure Figure 222 SPI Interface Signals Connection Type IO ...

Page 557: ...e Configure firmware button highlighted in the following figure to find the SPI driver information Figure 224 SPI Driver User s Guide 5 Click Generate Bitstream under Program Design to complete the fdb file generation 6 Double click the Export Firmware under Handoff Design for Firmware Development in the Libero SoC design flow window to generate the SoftConsole Firmware Project The SoftConsole fol...

Page 558: ... frame size for a specific target SPI slave device MSS_SPI_configure_slave_mode Configures a MSS SPI block for operations as a SPI slave device Data transfer functions MSS_SPI_set_slave_select Selects a specific slave by a MSS SPI master MSS_SPI_transfer_frame Used by a MSS SPI master to transmit and receive a frame up to 32 bits long MSS_SPI_transfer_block Used by MSS SPI masters to transmit and ...

Page 559: ... The MSS SPI_0 is configured as a master with the slave select line connected to the chip select of the external SPI Flash The following figure shows interfacing the external SPI flash to MSS SPI_0 Figure 226 Interfacing External SPI Flash to MSS SPI_0 Block Diagram Follow the instructions provided in the Design Flow page 520 to configure SPI_0 in the application The external SPI flash is the targ...

Page 560: ... SPI Peripheral Initialize the SPI instance SPI_0 by using MSS_SPI_init API SPI Master Mode Configuration Configure MSS SPI_0 in master mode by using MSS_SPI_configure_master_mode API The SPI peripheral generates a serial clock and data to the slave device The following parameters are required to configure SPI_0 so it will operate as a SPI Master SPI_0 instance data structure Target SPI slave SPI ...

Page 561: ...h Writer Protect Reset Source Description SOFT_RESET_CR RW P Bit SYSRESET_N Soft reset control LOOPBACK_CR RW P Register SYSRESET_N Loop back control PERIPH_CLK_MUX_SEL_CR RW P Register PORESET_N Peripheral clock MUX select Table 499 SPI Register Summary Register Name Address Offset R W Reset Value Description CONTROL 0x00 R W 0x80000102 Control register TXRXDF_SIZE 0x04 R W 0x04 Transmit and rece...

Page 562: ...asserted Allows multiple slaves to share a single slave select signal with a single master 29 BIGFIFO R W 0 Alters FIFO depth when frame size is 4 8 bits 0 FIFO depth is 4 frames 1 FIFO depth is 32 frames when frame size is 9 16 bits FIFO depth is 16 and when frame size is 17 32 bits FIFO depth is 8 28 CLKMODE R W 0 Specifies the methodology used to calculate the SPICLK divider 0 SPICLK 1 2CLK_GEN...

Page 563: ...he SPI is enabled 1 MODE R W 1 SPI implementation 0 Slave 1 Master default 0 ENABLE R W 0 Core enable 0 Disable default 1 Enable The core will not respond to external signals SPI_X_DI SPI_X_DO until this bit is enabled SPI_X_CLK is driven low and SPI_X_DOE_N and SPI_X_SS slave select are driven inactive Table 501 TXRXDF_SIZE Bit Number Name R W Reset Value Description 31 6 Reserved R W 0 Software ...

Page 564: ...tput enable is not asserted Allows multiple slaves to share a single slave select signal with a single master 11 TXFIFOEMPNXT R 0 Transmit FIFO empty on next read 10 TXFIFOEMP R 1 Transmit FIFO is empty 9 TXFIFOFULNXT R 0 Transmit FIFO full on next write 8 TXFIFOFUL R 0 Transmit FIFO is full 7 RXFIFOEMPNXT R 0 Receive FIFO empty on next read 6 RXFIFOEMP R 1 Receive FIFO empty 5 RXFIFOFULNXT R 0 Re...

Page 565: ...rved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 5 SSEND W Write one to clear the interrupt 4 CMDINT W Write one to clear the interrupt 3 TXCHUNDRUN W 0 Transmit channel under run 2 RXCHOVRFLW W 0 Receive channel over flow 1 RXRDYCLR W 0 Clears receive ready RX_RDY 0 TXDONECLR W 0 Clears transmit done TX_DON...

Page 566: ...PI Clock 0 76 900 000 0 76 900 000 1 38 450 000 1 38 450 000 2 19 225 000 2 25 633 333 33 3 9 612 500 3 19 225 000 4 4 806 250 4 15 380 000 5 2 403 125 5 12 816 666 67 6 1 201 562 5 6 10 985 714 29 7 600 781 25 7 9 612 500 8 300 390 625 8 8 544 444 444 9 150 195 312 9 7 690 000 10 75 097 656 10 6 990 909 091 11 37 548 828 11 6 408 333 333 12 18 774 414 12 5 915 384 615 13 9 387 207 13 5 492 857 14...

Page 567: ...ved bit should be preserved across a read modify write operation 5 SSEND R Indicates that SPI_X_SS x has gone inactive When this is high the interrupt is active 4 CMDINT R Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames SPI_X_SS x held active When this is high the interrupt is active 3 TXCHUNDDMSKINT R 0 Masked interrupt status Reading...

Page 568: ...ation 5 INTEN_SSEND R W Indicates that SPI_X_SS x has gone inactive 4 INTEN_CMD R W Indicates that the number of frames set by the CMDSIZE register have been received as a single packet of frames SPI_X_SS x held active 3 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read ...

Page 569: ...r time gaps between them This bit will be automatically cleared as soon as the core starts transmitting the frames 4 CLRFRAMECNT R W 0 No effect 1 Writing one clears the internal frame counter This bit always reads as zero The counter is also cleared when the core is disabled CTL1 or CTL2 are written that is the frame count limit changed 3 TXFIFORST R W 0 0 No effect 1 Writing one resets the Tx FI...

Page 570: ...he value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 0 CMDSIZE R W 0 Number of frames after SPI_SS 0 going active that the CMD interrupt should be generated This controls the RxCMD interrupt The internal counters count frames from SPI_SS 0 going low It automatically resets and starts counting...

Page 571: ...31 8 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 14 ACTIVE R 0 SPI is still transmitting the data 6 13 SSEL R 0 Current state of SPI_X_SS 0 5 3 TXUNDERRUN R 0 Transmit FIFO underflowed 4 2 RXOVERFLOW R 0 Receive FIFO overflowed 3 8 TXFIFOFU...

Page 572: ...n and arbitration Own slave address and general call address detection Second slave address detection System management bus SMBus timeout and real time idle condition counters Optional SMBus signals SMBSUS_N and SMBALERT_N which are controlled through the APB interface Input glitch or spike filters The following figure shows the I2 C peripherals within the MSS The I2 C peripherals are connected to...

Page 573: ...nternal APB interface clock APB_0_CLK and APB_1_CLK Refer to the Glitch Register page 561 for more information on Glitch register bit definitions 15 2 1 2 Arbitration and Synchronization Logic In Master Mode the arbitration logic monitors the data line If any other device on the bus drives the data line Low the I2 C peripheral immediately changes from Master Transmitter mode to Slave Receiver mode...

Page 574: ...ollowed by a direction bit which is decoded and acknowledged ACK by the slave Following the address phase multiple bytes can be transferred with an ACK for each byte The end of the transaction is signaled by a stop condition The stop condition is signaled by the SDA line asserted High while the SCL line is High When the I2 C peripheral is in a receiver Master or Slave mode it may acknowledge or ig...

Page 575: ...ssion speed control signal and is internally synchronized with the clock input BCLK is used to set the serial clock frequency from a clock sourced within the FPGA fabric when the CR 2 0 bits in the Control register are set to 0b111 0x7 Otherwise either APB_0_CLK or APB_1_CLK is used to determine the serial clock frequency The actual non stretched serial bus clock frequency can be calculated based ...

Page 576: ...I2 C peripheral is in Slave mode which is not addressed by the master I2 C peripheral checks for its own slave address and the general call address If one of these addresses is detected the I2 C peripheral is addressed by the master and then an interrupt is requested The I2 C peripheral can operate as a slave transmitter or a slave receiver 15 2 4 2 1 Transfer Example 1 The Cortex M3 processor set...

Page 577: ...to INTISR 7 INTISR 8 and INTISR 9 in the Cortex M3 processor NVIC controller All interrupt enable bits within the NVIC INTISR 4 through INTISR 9 correspond to bit locations 4 through 9 Enable SMBus interrupts I2C_X_SMBALERT and I2C_X_SMBSUS in the I2 C peripheral by setting the appropriate bits in the SMBUS register and clear the appropriate bit in the SMBus register in the interrupt service routi...

Page 578: ... section describes how to use I2 C in an application 15 3 1 Design Flow The following steps are used to enable the I2 C in the application by using Libero SoC 1 Enable I2C_0 and or I2C_1 instance by using the MSS configurator in the application as shown in the following figure Figure 232 Enable I2 C ...

Page 579: ... to an IO by using MSS I2C_0 Configurator as shown in the following figure Click the highlighted Users Guide button to find more information on I2 C configuration details Figure 233 MSS I2C Configurator 3 The I2C_0 interface signals in the MSS component are shown in the following figure Figure 234 I2 C Interface Signals ...

Page 580: ...artFusion2_MSS_I2C_Driver_UG as shown in the preceding figure Table 519 MSS I2C APIs Category API Description and Usage Initialization and configuration function MSS_I2C_init Initializes and configures the I2 C with MSS I2C s configuration as parameters I2 C master operation functions MSS_I2C_write Initiates an I2 C master write transaction MSS_I2C_read Initiates an I2C master read transaction MSS...

Page 581: ...ore information SMBus control functions MSS_I2C_smbus_init Initializes SMBus timeouts and status logics MSS_I2C_suspend_smbus_slave Forces slave devices into power down or suspend mode MSS_I2C_set_smbus_alert Used to force master communication by an I2 C slave device MSS_I2C_enable_smbus_irq Enables interrupt related to SMBus which can be either SMBSUS or SMBALERT interrupt MSS_I2C_disable_smbus_i...

Page 582: ...rite Operation Write data to the target slave device using MSS_I2C_write API This API ensures the presence of I2C_0 in Master mode for write transactions The following parameters are required to use the I2 C write API Target slave device address Ex EEPROM Data which is to be written to the target device Data size in bytes Read Operation Read data from the target slave device using MSS_I2C_read API...

Page 583: ...ed to enable the slave Read Operation Following are the steps to complete the read transaction Set the slave transmit buffer The data buffer is transmitted when the I2 C slave is the target of an I2 C read transaction Here use the MSS_I2C_set_slave_tx_buffer API Enable the slave MSS_I2C_enable_slave API can be used to enable the slave 15 3 2 3 Use Model 3 I2 C Loopback Mode I2C_0 and I2C_1 are int...

Page 584: ...a register Read write data to from the serial interface SLAVE0 ADR 0x0C R W 0x00 Slave0 address register Contains the primary programmable address of the I2 C peripheral SMBUS 0x10 R W 0b01X1X000 SMBus register Configuration register for SMBus timeout reset condition and for the optional SMBus signals SMBALERT_N and SMSBUS_N FREQ 0x14 R W 0x08 Frequency register Necessary for configuring real time...

Page 585: ...ere is a serviceable change in the Status register Once the register is updated the SI bit must be cleared by software The SI bit is directly readable through the APB INTERRUPT signal 2 AA R W 0 The assert acknowledge flag When AA 1 an acknowledge is returned when The own slave address is received The general call address is received when the GC bit in the address register is set A data byte is re...

Page 586: ...ansmitted ACK is received 0x10 A repeated START condition is transmitted Load SLA W 0 0 SLA W is transmitted ACK is received Load SLA R 0 0 SLA R is transmitted Core is switched to MST REC mode 0x18 SLA W is transmitted ACK is received Load data byte 0 0 0 Data byte is transmitted ACK is received No action 1 0 0 Repeated START is transmitted 0 1 0 STOP condition is transmitted STO flag is reset 1 ...

Page 587: ...STATUS Register Master Receiver Mode Status Code Status Data Register Action Control Register Bits Next Action Taken by Core STA STO SI AA 0x08 A START condition is transmitted Load SLA R 0 0 SLA R is transmitted ACK is received 0x10 A repeated START condition is transmitted Load SLA R 0 0 SLA R is transmitted ACK is received Load SLA W 0 0 SLA W is transmitted I2 C is switched to MST TRX mode 0x3...

Page 588: ...ister Action Control Register Bits Next Action Taken by Core STA STO SI AA 0x60 Own SLA W is received ACK is returned No action 0 0 0 Data byte is received and not ACK NACK is returned 0 0 1 Data byte is received and ACK is returned 0x68 Arbitration lost in SLA R W as master own SLA W is received ACK returned No action 0 0 0 Data byte is received and not ACK NACK is returned 0 0 1 Data byte is rec...

Page 589: ...dress DATA is received ACK returned Read data byte 0 0 0 Data byte is received and not ACK NACK is returned 0 0 1 Data byte is received and ACK is returned 0x98 Previously addressed with general call address DATA is received not ACK NACK returned Read data byte 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or general call address 0 0 0 1 Switched to not addressed SLV mode ow...

Page 590: ...tion is transmitted when the bus gets free 0xD8 25 ms SCL low time is reached device must be reset No action X 0 Slave must proceed to reset state by clearing the interrupt within 10ms according to SMBus specification v2 0 Table 527 STATUS Register Slave Transmitter Mode Status Code Status Data Register Action Control Register Bits Next Action Taken by Core STA STO SI AA 0xA8 Own SLA R is received...

Page 591: ...gnized START condition is transmitted when the bus gets free 0xC8 Last data byte is transmitted ACK is received No action 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or general call address 0 0 0 1 Switched to not addressed SLV mode own SLA or general call address is recognized 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or general call address STA...

Page 592: ... 0 A Start condition is transmitted when the bus gets free 0xF8 No relevant state information available SI 0 No Action No Action Idle 0x00 Bus error during MST or selected Slave modes No action 0 1 0 Only the internal hardware is affected in the MST or addressed SLV modes In all cases the bus is released and the state switched in non addressed Slave mode Stop flag is reset Table 529 Data Register ...

Page 593: ...ss bit 3 3 ADR2 R W 0 Own Slave0 address bit 2 2 ADR1 R W 0 Own Slave0 address bit 1 1 ADR0 R W 0 Own Slave0 address bit 0 0 GC R W 0 General call GC address acknowledge If the GC bit is set the general call address is recognized otherwise it is ignored Table 531 SMBus Register SMBUS Bit Number Name R W Reset Value Description 7 SMBus reset R W 0 Writing one to this bit forces the clock line Low u...

Page 594: ...o fabric It is used in Master Host mode if the slave devices want to force communication with a host 2 SMBus enable R W 0 0 SMBus timeouts and status logic disabled standard I2 C bus operation 1 SMBus timeouts and status logic enabled 1 SMBSUS interrupt enable R W 0 0 SMBSUS interrupt signal SMBS disabled 1 SMBSUS interrupt signal SMBS enabled 0 SMBALERT interrupt enable R W 0 0 SMBALERT interrupt...

Page 595: ...escription 7 0 GlitchReg_Num R W 0x03 This read write register is used to adjust the input glitch filter length Depending on the application the glitch filter is used to suppress spikes between 3 and 21 APB interface clock cycles Number or length of shift register filter is set to value from 3 to 21 Table 534 Slave1 Address Register SLAVE1 ADR Bit Number Name R W Reset Value Description 7 ADR6 R W...

Page 596: ... M3 processor in Input mode The reset state of the GPIOs is configurable The GPIOs can be selectively reset by either the hard reset power on reset user reset from the fabric or the soft reset from the SYSREG block The MSS GPIO block features mentioned above can be configured using Libero SoC software Figure 239 GPIO Connected on APB Slave in MSS AHB Bus Matrix 10 x 7 AHB To AHB Bridge with Addres...

Page 597: ... to the Cortex M3 processor This can be configured as an edge triggered on rising edge falling edge or both edges or as a level sensitive active low or active high interrupt The interrupt is latched in the GPIO_IRQ register and is accessible through the APB bus as shown in Table 536 page 566 In Edge sensitive mode GPIO_IRQ register is cleared either by disabling the interrupt or writing a logic 1 ...

Page 598: ...i INT i GPIO_i_IN GPIO_i_OUT GPIO_i_OE GPIO_OUT Reg Interrupt Reg GPIO_IRQ i Interrupt Generate Logic I O MUX Input Enable EN_IN_i EN_I NT_i EN_OUT_i TYPES_INT_i CONFIG_X Configuration register 32bit Interrupt Types Output Enable Interrupt Enable APB INTERFACE Sync GPIO_IN Reg 0 D Q MSIO D Q D Q 0 31 8 1 2 3 4 5 6 7 0 D Q ...

Page 599: ...gisters Table 535 GPIO_X_CFG Bit Number Name Type Reset Value Description GPIO_X_CFG 31 8 Reserved R W 0h000000 Reserved GPIO_X_CFG 7 5 TYPES_INT_I R W 0b000 Input interrupt type configuration Refer Figure 242 page 565 for Bit definitions GPIO_X_CFG 4 Reserved R W 0b0 Reserved GPIO_X_CFG 3 EN_INT_i R W 0b0 0 Interrupt disabled 1 Interrupt enabled GPIO_X_CFG 2 GPIO_i_OE R W 0b0 0 Disable output buf...

Page 600: ...GPIO_8 INTISR 59 GPIO_INT 9 GPIO_9 Interrupt from GPIO_9 INTISR 60 GPIO_INT 10 GPIO_10 Interrupt from GPIO_10 INTISR 61 GPIO_INT 11 GPIO_11 Interrupt from GPIO_11 INTISR 62 GPIO_INT 12 GPIO_12 Interrupt from GPIO_12 INTISR 63 GPIO_INT 13 GPIO_13 Interrupt from GPIO_13 INTISR 64 GPIO_INT 14 GPIO_14 Interrupt from GPIO_14 INTISR 65 GPIO_INT 15 GPIO_15 Interrupt from GPIO_15 INTISR 66 GPIO_INT 16 GPI...

Page 601: ...t reset signals from the SYSREG block to reset all the 32 GPIO output registers Each soft reset signal resets the GPIO output byte 8 GPIO_OUT registers Table 540 page 576 shows the soft reset signals from the SYSREG block Each GPIO output byte reset is enabled by the control signals from the SYSREG block The reset enable feature for each GPIO output byte is used to hold the GPIO_OUT register value...

Page 602: ...nd shows different options available for configuring GPIO The MSS GPIO is disabled by default in MSS configurator when the Libero SoC project is created Following pages describe the steps to be used to configure in Libero SoC Step 1 Enable the MSS GPIO in the Libero SoC project using MSS configurator as shown in the following figure Figure 243 Enable GPIO in MSS Configurator ...

Page 603: ...llowing figure Set Reset definition Used to initialize the GPIOs GPIO assignment 3 programming fields associated with each GPIO Direction Selects Input Output Bidirectional or Tristate mode Package pin Shows the MSIO pin associated with the GPIO Connectivity Selects IO_A IO_B MSIO or FABRIC_A FABRIC_B Advanced options When enabled shows the possibility of connecting the GPIO input or GPIO output t...

Page 604: ... 3 Configuring MSS GPIOs as Input Output Tristate and Bi directional There are four modes of MSS GPIO which can be configured using Libero SoC Input Output Bi directional Tristate To configure a GPIO as an interrupt configure GPIO as an input in Libero SoC Enable the interrupt in SoftConsole using MSS GPIO application program interfaces APIs Refer to the Use Model 1 Configuring GPIOs to Act as Int...

Page 605: ...e 246 Configuring GPIOs as Input Output Tristate or Bi directional Connectivity Preview GPIOs have access to IO_A or IO_B MSIOs If an MSIO is used by any shared peripheral GPIOs cannot access those particular MSIOs GPIOs can be connected directly to the fabric by selecting FABRIC_A or FABRIC_B GPIOs connecting to MSIOs can also be shared with fabric using the Advanced Options of the MSS GPIO confi...

Page 606: ...configured GPIO signals are shown in the following figure Figure 248 GPIO Signals Step 4 To generate a component click the Generate Component shortcut in MSS configurator or select SmartDesign Generate Component The firmware driver folder and SoftConsole workspace will be included in the design project Step 5 Click Generate Bitstream under Program Design to complete the fdb file generation ...

Page 607: ...efined state using the MSS_GPIO_init API in SoftConsole or Libero SoC 3 Configure GPIOs as inputs by using the MSS_GPIO_config API in SoftConsole or Libero SoC 4 Use the interrupt API MSS_GPIO_enable_irq to dynamically configure the input from the MSIO to interrupt the Cortex M3 processor Use API MSS_GPIO_disable_irq to disable the interrupt to the Cortex M3 processor 5 Each GPIO input can also be...

Page 608: ... GPIO block is 0x40013000 The address offset of each MSS GPIO register is provided in the following table The table also includes configuration input and output registers Table 538 MSS GPIO Register Map Register Name Address Offset Register Type Reset Value Description GPIO_0_CFG 0x00 R W 0x0 Configuration register for GPIO 0 GPIO_1_CFG 0x04 R W 0x0 Configuration register for GPIO 1 GPIO_2_CFG 0x0...

Page 609: ...on register for GPIO 23 GPIO_24_CFG 0x60 R W 0x0 Configuration register for GPIO 24 GPIO_25_CFG 0x64 R W 0x0 Configuration register for GPIO 25 GPIO_26_CFG 0x68 R W 0x0 Configuration register for GPIO 26 GPIO_27_CFG 0x6C R W 0x0 Configuration register for GPIO 27 GPIO_28_CFG 0x70 R W 0x0 Configuration register for GPIO 28 GPIO_29_CFG 0x74 R W 0x0 Configuration register for GPIO 29 GPIO_30_CFG 0x78...

Page 610: ...RW P Register PORESET_N Configures GPIO system reset GPIN_SRC_SEL_CR 0x5C RW P Register PORESET_N Used to generate a GPIO input signal Table 540 SOFT_RESET_CR Bit Number Name Reset Value Description 24 MSS_GPOUT_31_24_SOFTRESET 0x1 0 Releases GPIO_OUT 31 24 from reset 1 Keeps GPIO_OUT 31 24 in reset 23 MSS_GPOUT_23_16_SOFTRESET 0x1 0 Releases GPIO_OUT 23 16 from reset 1 Keeps GPIO_OUT 23 16 in res...

Page 611: ... 16 to 0 or 1 after reset 1 MSS_GPIO_15_8_DEF 0x1 Used to initialize GPIO bank 15 8 to 0 or 1 after reset 0 MSS_GPIO_7_0_DEF 0x1 Used to initialize GPIO bank 7 0 to 0 or 1 after reset Table 542 LOOPBACK_CR Bit Number Name Reset Value Description 31 4 Reserved 0 Reserved 3 MSS_GPIOLOOPBACK 0 Controls whether internal loopback on the MSS GPIO is enabled Allowed values 0 No internal loopback for MSS ...

Page 612: ...is reset by either power on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric 1 The GPIO 23 16 is reset by the soft reset signal MSS_GPIO_23_16_SOFT_RESET 1 MSS_GPIO_15_8_SYSRESET_SEL 0 0 The GPIO 15 8 is reset by either power on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric 1 The GPIO 15 8 is reset by the soft reset signal MSS_GPIO_15_8_SOFT_RESET 0 MSS_GPIO_7_0_SYSRESET_SEL 0...

Page 613: ...DATAO 3 GPIO_OUT 0 IN_B F2H_SCP 11 OE SDA_1_OUT NDATAOE GPIO_OE 0 OUT_A H2F_A 11 OUT_B H2F_B 11 Table 547 IOMUX CELL 12 I O Pad Ports IOMUXCELL Interface I2C_1 USB Controller GPIO 1 FPGA Fabric IN SCL_1_IN USBA_DATAI 4 GPIOA_IN 1 IN_A F2H_GPIN 12 OUT GND DATAO 4 GPIO_OUT 1 IN_B F2H_SCP 12 OE SCL_1_OUT NDATAOE GPIO_OE 1 OUT_A H2F_A 12 OUT_B H2F_B 11 Table 548 IOMUX CELL 13 I O Pad Ports IOMUXCELL I...

Page 614: ...4 OUT GND DATAO 1 GPIO_OUT 3 IN_B F2H_SCP 14 OE GND NDATAOE GPIO_OE 3 OUT_A H2F_A 14 OUT_B H2F_B 14 Table 550 IOMUX CELL 15 I O Pad Ports IOMUXCELL Interface CAN USB Controller GPIO 4 FPGA Fabric IN NC USBA_DATAI 2 GPIOA_IN 4 IN_A F2H_GPIN 15 OUT CAN_TB_EBL_n DATAO 2 GPIO_OUT 4 IN_B F2H_SCP 15 OE VDD NDATAOE GPIO_OE 4 OUT_A H2F_A 15 OUT_B H2F_B 15 Table 551 IOMUX CELL 16 I O Pad Ports IOMUXCELL In...

Page 615: ...UT 6 IN_B F2H_SCP 17 OE SPIOEN_0 VDD GPIO_OE 6 OUT_A H2F_A 17 OUT_B H2F_B 17 Table 553 IOMUX CELL 18 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 7 FPGA Fabric IN SPISSI_0_IN USBA_NXT GPIOA_IN 7 IN_A F2H_GPIN 18 OUT SPISS_0_OUT 0 GND GPIO_OUT 7 IN_B F2H_SCP 18 OE SPI_0_MASTER GND GPIO_OE 7 OUT_A H2F_A 18 OUT_B H2F_B 18 Table 554 IOMUX CELL 19 I O Pad Ports IOMUXCELL Interface SPI_0 ...

Page 616: ...OUT_B H2F_B 20 Table 556 IOMUX CELL 21 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 10 FPGA Fabric IN NC USBA_DATAI 7 GPIOA_IN 10 IN_A F2H_GPIN 21 OUT SPISS_0_OUT 3 DATAO 7 GPIO_OUT 10 IN_B F2H_SCP 21 OE SPI_0_MASTER NDATAOE GPIO_OE 10 OUT_A H2F_A 21 OUT_B H2F_B 21 Table 557 IOMUX CELL 22 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 19 FPGA Fabric IN NC NC GPIOA_IN 19...

Page 617: ...0_OUT 6 GND GPIO_OUT 21 IN_B GND OE SPI_0_MASTER GND GPIO_OE 21 OUT_A H2F_A 24 OUT_B NC Table 560 IOMUX CELL 25 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 22 FPGA Fabric IN NC NC GPIOA_IN 22 IN_A GND OUT SPISS_0_OUT 7 GND GPIO_OUT 22 IN_B GND OE SPI_0_MASTER GND GPIO_OE 22 OUT_A H2F_A 25 OUT_B NC Table 561 IOMUX CELL 26 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 1...

Page 618: ...28 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 13 FPGA Fabric IN SPISSI_1_IN NC GPIOA_IN 13 IN_A F2H_GPIN 28 OUT SPISS_1_OUT 0 GND GPIO_OUT 13 IN_B F2H_SCP 28 OE SPI_1_MASTER GND GPIO_OE 13 OUT_A H2F_A 28 OUT_B H2F_B 28 Table 564 IOMUX CELL 29 I O Pad Ports IOMUXCELL Interface SPI_0 USB Controller GPIO 14 FPGA Fabric IN NC NC GPIOA_IN 14 IN_A F2H_GPIN 29 OUT SPISS_1_OUT 1 GND GPIO_...

Page 619: ...1 OUT_B H2F_B 31 Table 567 IOMUX CELL 32 I O Pad Ports IOMUXCELL Interface SPI_1 USB Controller GPIO 17 FPGA Fabric IN NC NC GPIOA_IN 17 IN_A GND OUT SPISS_1_OUT 4 GND GPIO_OUT 17 IN_B GND OE SPI_1_MASTER GND GPIO_OE 17 OUT_A H2F_A 32 OUT_B NC Table 568 IOMUX CELL 33 I O Pad Ports IOMUXCELL Interface SPI_1 USB Controller GPIO 18 FPGA Fabric IN NC NC GPIOA_IN 18 IN_A GND OUT SPISS_1_OUT 5 GND GPIO_...

Page 620: ...F_A 35 OUT_B NC Table 571 IOMUX CELL 36 I O Pad Ports IOMUXCELL Interface MMUART_1 USB Controller GPIO 11 FPGA Fabric IN NC NC GPIOB_IN 11 IN_A F2H_GPIN 36 OUT RTS_1_OUT GND GPIO_OUT 11 IN_B F2H_SCP 36 OE VDD GND GPIO_OE 11 OUT_A H2F_A 36 OUT_B H2F_B 36 Table 572 IOMUX CELL 37 I O Pad Ports IOMUXCELL Interface MMUART_1 USB Controller GPIO 12 FPGA Fabric IN NC NC GPIOB_IN 12 IN_A GND OUT DTR_1_OUT ...

Page 621: ...C Table 575 IOMUX CELL 40 I O Pad Ports IOMUXCELL Interface MMUART_1 USB Controller GPIO 15 FPGA Fabric IN RI_1_IN NC GPIOB_IN 15 IN_A GND OUT GND GND GPIO_OUT 15 IN_B F2H_SCP 40 OE VDD GND GPIO_OE 15 OUT_A NC OUT_B NC Table 576 IOMUX CELL 41 I O Pad Ports IOMUXCELL Interface MMUART_1 USB Controller GPIO 16 FPGA Fabric IN DCD_1_IN NC GPIOB_IN 16 IN_A GND OUT GND GND GPIO_OUT 16 IN_B F2H_SCP 41 OE ...

Page 622: ... H2F_A 43 OUT_B H2F_B 43 Table 579 IOMUX CELL 44 I O Pad Ports IOMUXCELL Interface MMUART_1 USB Controller GPIO 26 FPGA Fabric IN RXD_1 _IN USBC_DATAI 3 GPIOB_IN 26 IN_A F2H_GPIN 44 OUT GND DATAO 3 GPIO_OUT 26 IN_B F2H_SCP 44 OE GND NDATAOE GPIO_OE 26 OUT_A H2F_A 44 OUT_B H2F_B 44 Table 580 IOMUX CELL 45 I O Pad Ports IOMUXCELL Interface MMUART_0 USB Controller GPIO 17 FPGA Fabric IN NC USBC_DATAI...

Page 623: ...47 OUT_B H2F_B 47 Table 583 IOMUX CELL 48 I O Pad Ports IOMUXCELL Interface MMUART_0 USB Controller GPIO 20 FPGA Fabric IN DSR_0_IN NC GPIOB_IN 20 IN_A F2H_GPIN 48 OUT GND GND GPIO_OUT 20 IN_B F2H_SCP 48 OE GND GND GPIO_OE 20 OUT_A H2F_A 48 OUT_B H2F_B 48 Table 584 IOMUX CELL 49 I O Pad Ports IOMUXCELL Interface MMUART_0 USB Controller GPIO 21 FPGA Fabric IN RI_0_IN NC GPIOB_IN 21 IN_A F2H_GPIN 49...

Page 624: ... Table 587 IOMUX CELL 52 I O Pad Ports IOMUXCELL Interface MMUART_0 USB Controller GPIO 28 FPGA Fabric IN RXD_0_IN NC GPIOB_IN 28 IN_A F2H_GPIN 52 OUT GND STP GPIO_OUT 28 IN_B F2H_SCP 52 OE GND VDD GPIO_OE 28 OUT_A H2F_A 52 OUT_B H2F_B 52 Table 588 IOMUX CELL 53 I O Pad Ports IOMUXCELL Interface MMUART_0 USB Controller GPIO 29 FPGA Fabric IN MMUART0_SCK_IN USBC_NXT GPIOB_IN 29 IN_A F2H_GPIN 53 OUT...

Page 625: ...ce I2C_0 USB Controller GPIO 31 FPGA Fabric IN SCL_0_IN USBC_DATAI 1 GPIOB_IN 31 IN_A F2H_GPIN 55 OUT GND DATAO 1 GPIO_OUT 31 IN_B F2H_SCP 55 OE SCL_0_OUT NDATAOE GPIO_OE 31 OUT_A H2F_A 55 OUT_B H2F_B 55 Table 591 IOMUX CELL 56 I O Pad Signals IOMUXCELL Interface I2C_0 USB Controller GPIO 23 FPGA Fabric IN NC USBD_DATAI 7 GPIOB_IN 23 IN_A GND OUT GND DATAO 7 GPIO_OUT 23 IN_B GND OE GND NDATAOE GPI...

Page 626: ...clock 50 MHz RC oscillator is different from advanced peripheral bus APB clock 8 byte transmit FIFO 8 byte receive FIFO Flow control RX to TX channels between microcontroller subsystem MSS COMM_BLK and system controller COMM_BLK MSS COMM_BLK to peripheral direct memory access PDMA channel Frame and or command marker 9th bit used as frame start or command marker Allows command and data sequences to...

Page 627: ...r Whenever the Cortex M3 processor writes a character into the COMM_BLK it is transmitted to the receiving side of the COMM_BLK and an interrupt is asserted to the system controller AHB Bus Matrix MS5 MM8 eSRAM_0 eSRAM_1 eNVM_0 eNVM_1 System Controller Cache Controller S D IC ARM Cortex M3 Processor S D I MSS DDR Bridge PDMA MS0 MS1 MS3 MS2 MM9 MM0 MM1 MM2 MS6 MM3 MM7 USB OTG AHB To AHB Bridge wit...

Page 628: ... transfers from embedded nonvolatile memory eNVM to the COMM_BLK to facilitate the initialization of fabric SRAMs Micro SRAM uSRAM and Large SRAM LSRAM 17 2 2 Frame Command Marker The COMM_BLK allows the data that is being transferred to be marked as a command or data byte It is expected that a software protocol transfers packets of data between the COMM_BLK blocks To allow the receiver to correct...

Page 629: ... must be enabled by setting the appropriate bits in the interrupt enable register Clear the appropriate bit in the Interrupt Enable Register when servicing the COMMS_INT to prevent a reassertion of the interrupt 17 2 6 COMM_BLK Initialization The COMM_BLK peripheral can be initialized by configuring the COMM_BLK Control Register and SOFT_RESET_CR system register The initialization sequence is as f...

Page 630: ... is generated Generate the component by clicking Generate Component or by selecting SmartDesign Generate Component from the menu the firmware and SoftConsole workspace are created in the project folder The following figure shows the system services driver folder hierarchy Figure 253 System Services Driver Folder Hierarchy 17 3 1 1 APIs The following table lists the APIs for the COMM_BLK Note Micro...

Page 631: ...97 through Table 600 on page 600 show the COMM_BLK Register Map 17 4 COMM_BLK Configuration Registers The COMM_BLK base address resides at 0x40016000 and extends to address 0x40016FFF in the Cortex M3 processor memory map The following table summarizes the control and status registers for the COMM_BLK Table 593 COMM_BLK Register Map Register Name Address Offset R W Reset Value Description CONTROL ...

Page 632: ...n set to 0 the flags indicate that a byte can be read and when set to 1 it indicates that a word can be read 2 SIZETX R W 0 Sets the number of bytes that each APB transfer writes into the TX FIFO 0 1 Byte 1 4 Bytes 32 bits This setting effects the behavior of TxRDY signal and TXTOKAY When set to 0 the flags indicate that a byte can be written and when set to 1 it indicates that a word can read be ...

Page 633: ...t Bit 8 on DATA is set to 0 indicating that it is data Writes to this register automatically set the SIZETX to 0 1 byte and reads set the SIZERX to 0 1 byte 4 SIIDONE R W 0 Indicated that the transfer to SII Bus is complete Write 1 to clear 3 UNDERFLOW R W 0 Receive Overflow Indicates that the receive FIFO was read when empty Write 1 to clear 2 OVERFLOW R W 0 Transmit Overflow Indicates that the T...

Page 634: ...it 7 indicates that this byte is a command 17 5 7 Frame Command Word Register This register writes a word 32 bits to the Transmit FIFO or reads a word from the Receive FIFO If the Transmit FIFO has less than four spaces available at the time of a write an OVERFLOW will be set in STATUS register Similarly if Receive FIFO has less than four bytes available at the time of a read an UNDERFLOW will be ...

Page 635: ...atrix through the APB_1 interface Figure 254 Microcontroller Subsystem Showing RTC AHB Bus Matrix eSRAM_0 System Controller Cache Controller S D IC ARM Cortex M3 Processor S D I MSS DDR Bridge PDMA MS6 MM3 AHB To AHB Bridge with Address Decoder USB OTG HPDMA MDDR APB_0 SYSREG Triple Speed Ethernet MAC FIC_0 MM4 MS4 MS2 MS3 MS0 MS5 MS1 MM5 MM6 MM7 MM8 MM2 MM1 MM0 MM9 IDC D S eNVM_0 eNVM_1 eSRAM_1 F...

Page 636: ...escaler must be programmed to generate a 1 Hz strobe to the RTC In Binary mode Clock mode 0 the prescaler can be programmed as required in the application 18 2 1 2 RTC Counter The RTC counter keeps track of seconds minutes hours days weeks and years when in Calendar mode and for this purpose it requires a 43 bit counter When counting in Binary mode the 43 bit register is treated as a linear up cou...

Page 637: ...ck inputs RTCCLK This is used to clock the RTC PCLK This is used for the CPU interface Hour 5 0 23 0 31 0 0 Day 5 1 31 auto adjust by month and year 0 31 1 0 Month 4 1 12 0 15 1 0 Year 8 0 255 Year 2000 to 2255 0 255 0 year 2000 0 Weekday 3 1 7 0 7 1 0 Week 6 1 52 0 63 1 0 Table 602 RTC Interface Signals Port MSB LSB Dir Description PCLK in APB interface clock PRESETN in Processor reset PADDR 6 0 ...

Page 638: ...unter is incremented as the day of week goes from 7 to 1 18 2 3 2 RTC_MATCH Status Bit and Output The RTC_MATCH status bit and output is asserted whenever the Alarm system is enabled and a match occurs In Calendar mode it is asserted for a 1 second period while the alarm condition is valid The output is synchronous to the rising edge of RTCCLK The RTC_MATCH output signal can also be driven to the ...

Page 639: ...ibes how to use the RTC in an application 18 3 1 Design Flow The following steps are used to enable the RTC in the application 1 Enable RTC by using the MSS configurator in the application as shown in the following figure Figure 256 Enabling RTC in the Libero SOC Design MSS Configurator ...

Page 640: ...TC_WAKEUP interrupt to the FPGA fabric the Cortex M3 processor and the system controller The interrupt to be enabled can be selected using this configurator Select the RTC_MATCH The RTC_MATCH status bit and output is asserted whenever the Alarm system is enabled and a match occurs In Calendar mode it is asserted for a 1 second period while the alarm condition is valid The output is synchronous to ...

Page 641: ...o be downloaded from the Microsemi firmware catalog The following table lists the APIs for RTC For more information on the APIs refer to the SmartFusion2_MSS_RTC_Driver_UG shown in the preceding figure Table 603 RTC APIs Category API Description and Usage Initialization MSS_RTC_init Initializes RTC Setting and reading the RTC counter current value MSS_RTC_set_calendar_count Sets new calendar value...

Page 642: ...alue RTC generates the interrupt Clear the interrupt 8 Stop RTC increment using the MSS_RTC_stop function Note The MSS RTC does not support full behavioral simulation models Refer to SmartFusion2 MSS BFM Simulation User Guide for more information 18 4 RTC Register Map The Register Map for the RTC is shown in Table 606 page 609 Note In this peripheral all the register writes should be a WORD operat...

Page 643: ...alendar Mode Counter Counts Size Bits Bits in Counter Reset Value Seconds 0 59 6 5 0 0 Minutes 0 59 6 11 6 0 Hours 0 23 5 16 12 0 Day 1 31 5 21 17 1 Month 1 12 5 25 22 1 Year 0 255 8 33 26 0 Weekday 1 7 3 36 34 7 Week 1 52 6 42 37 1 Table 605 Register Bit Allocation Clock Mode Date Time Alarm Compare Register Bits Description 0 Lower 31 0 Binary Count 31 0 Upper 10 0 Binary Count 42 32 1 Lower 7 0...

Page 644: ...lue It indicates the value of the RTC_MATCH output This is normally active for 1 second while the current time matches the alarm setting 6 Download W 0 Writing a 1 causes the current RTC value to be downloaded to the date time upload registers initializing the upload value to the current time This does not require any synchronization and takes place immediately 5 Upload R W 0 When 1 is written the...

Page 645: ...n 4 Wake_reset_ps R W 0 When a wakeup occurs resets the Prescaler 3 Wake_continue R W 0 When a wakeup occurs continues counting otherwise the counters including the Prescaler stop until wake up is cleared 2 Wake_reset R W 0 When a wake up occurs resets the RTC 1 Wake_enable R W 0 Enables the wakeup interrupt output 0 Clock_mode R W 0 0 Binary counter 1 Calendar mode Table 609 Prescaler Bit Number ...

Page 646: ... the compare bits on the alarm time on write and returns the compare value on read 0 Bit is ignored 1 Bit is compared 0x18 31 0 Compar e Upper R W 0 Sets the compare bits on the alarm time on write and returns the compare value on read 0 Bit is ignored 1 Bit is compared Table 611 Date and Time Address Offset Register Name Bit Numbers Name R W Reset Value Description 0x20 Date Time 31 0 Datetime Lo...

Page 647: ...current date time value It is possible that the date time may increment between reads For writing all fields 0 50 6C must be written The control register upload bit uploads data to the RTC These registers are for use when clock_mode 1 0x54 5 0 Minutes R W 0 0x58 4 0 Hours R W 0 0x5C 4 0 Day R W 0 0x60 4 0 Month R W 0 0x64 7 0 Year R W 0 0x68 2 0 Weekday R W 0 0x6C 5 0 Week R W 0 Table 612 The RTC_...

Page 648: ...s details of the MSS Timer peripherals are connected to the AHB bus matrix through the APB_0 interface Figure 261 MSS Showing Timer Peripherals 19 2 Functional Description This section provides detailed description of the timer 19 2 1 Architecture Overview The timer is an APB_0 slave that provides two programmable interrupt generating 32 bit decrementing counters as shown in the following figure A...

Page 649: ...Resets Timer resets to zero on power up and is held in reset until enabled Libero SoC software can reset the Timer by writing to bit 6 of SOFT_RESET_CR in the SYSREG block Soft reset bit definitions are provided in the following table Table 613 Timer Interface Signals Name Type Width Description TIMER1INT Output 1 Active high interrupt from counter 1 If enabled this interrupt is asserted when coun...

Page 650: ...eached zero In effect an interrupt is lost It can continue indefinitely as long as the counter is enabled in Periodic mode and interrupts are not cleared Writing to the TIMxLOADVAL register at any time causes the counter to be loaded immediately with the value written and if enabled it will continue counting down from the new value If the TIMx_BGLOADVAL background load value register is written th...

Page 651: ... be written to first followed by the lower 32 bits It occurs as a two step process first the upper 32 bits are written and then this value is stored in temporary register When you write the lower 32 bits the upper 32 bits are simultaneously written to the destination register If a read is done on the target register before the write to the lower 32 bits is done the functional value of the target r...

Page 652: ...igure 264 Block Diagram 64 Bit Mode APB Bus TIMxBGLOADVAL TIMxLOADVAL TIMERxINT TIMERx TIMxMODE TIMxENABLE PCLK TIMxVALUE APB Bus APB Bus APB Bus TIM64BGLOADVAL TIM64BGLOADVAL TIM64LOADVAL TIM64LOADVAL TIMER1INT TIMER1INT TIMER1 TIMER1 TIM64MODE TIM64ENABLE PCLK TIM64MODE TIM64ENABLE PCLK ...

Page 653: ...ers Figure 265 Timer Driver User Guide 3 Click Generate Bitstream under Program Design to complete fdb file generation Double click Export Firmware under Handoff Design for Firmware Development in the Libero SoC design flow window to generate the SoftConsole Firmware Project The SoftConsole folder contains the mss_timer firmware driver The firmware driver mss_timer mss_timer h which provides a set...

Page 654: ...mmediate Loads the values passed by the load_value_u and load_value_l parameters into the 64 bit timer down counter MSS_TIM64_load_background Specify the 64 bit value that will be reloaded into the 64 bit timer down counter the next time the counter reaches zero MSS_TIM64_get_current_value Read the current value of the 64 bit timer down counter MSS_TIM64_start Enables the 64 bit timer MSS_TIM64_st...

Page 655: ...e 0x186A0 3 Enable Timer 1 interrupt using MSS_TIM1_enable_irq 4 Start the Timer using MSS_TIM1_start 5 Whenever the counter reaches zero it generates an interrupt 6 Clear the interrupt using MSS_TIM1_clear_irq and stop the Timer using MSS_TIM1_stop Notes MSS_TIM1_clear_irq function must be called as a part of implementation of the Timer1_IRQHandler Timer 1 interrupt service routine ISR in order t...

Page 656: ...escription TIM1_VAL TIMx_VAL 0x00 R 0 Current value of Timer1 TIM1_LOADVAL TIMx_LOADVAL 0x04 R W 0 Load value for Timer1 TIM1_BGLOADVAL TIMx_BGLOADVAL 0x08 R W 0 Background load value for Timer1 TIM1_CTRL TIMx_CTRL 0x0C R W 0 Control register for Timer1 TIM1_RIS TIMx_RIS 0x10 R W 0 Timer 1 raw interrupt status TIM1_MIS TIMx_MIS 0x14 R 0 Timer 1 masked interrupt status TIM2_VAL TIMx_VAL 0x18 R 0 Cu...

Page 657: ...lue When operating in Periodic mode the value in this register is used to reload the counter when the counter decrements to zero This register is overwritten if the TIMx_BGLOADVAL register is written but the counter will not be updated with the new value in this case In Periodic mode TIMx_LOADVAL always stores the value which is loaded into the counter Writing or reading this register when the Tim...

Page 658: ...s zero the counter stops counting To start the counter again you must load TIMx_LOADVAL with a non zero value or set the Timer to Periodic mode by clearing TIMxMODE to 0 Writing this register when the Timer is set to 64 bit mode has no effect Reading this register when the Timer is set to 64 bit mode returns the reset value 0 TIMxENABLE R W 0 Timer x enable 0 Timer x disabled 1 Timer x enabled Wri...

Page 659: ..._VAL_U This register is read only writes have no effect Reading this register when the Timer is set to 32 bit mode returns the reset value Table 624 TIM64_VAL_L Bit Number Name R W Reset Value Description 31 0 TIM64_VAL_L R 0 This register holds the current value of the lower 32 bits of the 64 bit count value for the Timer This register is read only writes have no effect When reading from this reg...

Page 660: ...ode is selected the values in the TIM64_LOADVAL_L and TIM64_LOADVAL_U are loaded into the counter when the counter decrements to zero Writing this register when the Timer is set to 32 bit mode has no effect Reading this register when the Timer is set to 32 bit mode returns the reset value Table 627 TIM64_BGLOADVAL_U Bit Number Name R W Reset Value Description 31 0 TIM64_BGLOADVAL_ U R W 0 This reg...

Page 661: ...tion 31 3 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 TIM64INTEN R W 0 Timer 64 interrupt enable When the counter reaches zero an interrupt is signaled to the Cortex M3 processor NVIC 0 Timer 64 interrupt disabled 1 Timer 64 interrupt enabl...

Page 662: ...mber Name R W Reset Value Description 31 1 Reserved R 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 TIM64_MIS R 0 Timer 64 masked interrupt status This read only bit is a logical AND of the TIM64RIS and TIM64INTEN bits The TIMER64INT output from the Timer...

Page 663: ...ex M3 processor enters the debug state The watchdog timer can be configured to generate a wake up interrupt when the Cortex M3 is in sleep mode As shown in the following figure the watchdog timer is connected to the AHB bus matrix through the APB_0 interface Figure 267 Microcontroller Subsystem Showing Watchdog Timer AHB Bus Matrix eSRAM_0 System Controller Cache Controller S D IC ARM Cortex M3 Pr...

Page 664: ...at must be refreshed at regular intervals by the Cortex M3 processor If not refreshed the counter will time out This either causes a system reset or generates an interrupt to the processor depending on the value of the WDOGMODE bit as defined in the WDOG_CR Register The WDOG_CR register is one of the system registers that helps to configure the watchdog timer In normal operation the generation of ...

Page 665: ...o it This effectively means that there is a lower limit on the value that can be written to the counter After refreshing at least 64 RCOSCCLK clock ticks 0 00128ms for Vdd 1 2 V are required before the counter times out The purpose of this feature is to prevent a watchdog timer reset interrupt from occurring immediately after or during refresh in the case where a very low value has been written to...

Page 666: ... Watchdog Timer Behavior During Microcontroller Modes Device Programming and Flash Freeze This section describes the behavior of the watchdog timer in the Cortex M3 processor modes and when the device is being programmed 20 2 3 2 1 Cortex M3 Processor in Debug State The halted output from the Cortex M3 is asserted when the processor is in debug mode and this signal is fed to the Watchdog When the ...

Page 667: ...ontroller under certain conditions such as when programming the eNVM When the PROGRAMMING port is asserted the watchdog timer counting is paused When the PROGRAMMING is de asserted the watchdog timer behaves as if it has just come out of reset 20 2 3 2 4 Flash Freeze During Flash Freeze the watchdog timer continues to operate unless the Cortex M3 processor enters Sleep mode In Sleep mode the watch...

Page 668: ...low The following steps are used to enable the WatchDog Timer in the application 1 Enable the watchdog timer by using the MSS configurator in the application as shown in the following figure Figure 270 Enabling Watchdog Timer in the Libero SOC Design MSS Configurator ...

Page 669: ...ose WD_TIMEOUT WDOGTIMEOUTINT port to Fabric check box Refresh Count Use the Refresh Count option to set the WDOGLOAD register value Flash Bits at POR or when the device is reset DEVRST_N is asserted de asserted Refresh Count value should be higher or equal to the default value which is 0x1800000 Counter Threshold Use the Counter Threshold option to set the value for WDOGMVRP System register It is...

Page 670: ...e catalog The following table lists the APIs for Watchdog Timer For more information on the APIs refer to the SmartFusion2_MSS_Watchdog_Driver_UG Table 634 Watchdog Timer APIs Category API Description and Usage Initialization MSS_WD_init Initializes Watchdog Timer Reading the watchdog timer current value and status MSS_WD_current_value Returns the current value of the watchdog s down counter MSS_W...

Page 671: ...et is resetting as part of a watchdog timeout 6 Call MSS_WD_clear_timeout_event function after a call to MSS_WD_timeout_occured function to clear the hardware s report of a time out event 20 3 2 2 Use Model 2 The steps below are used to generate a watchdog timer interrupt on timeout 1 Enable the watchdog timer in MSS configurator of your Libero project 2 Select timeout behavior as interrupt in the...

Page 672: ...itted This register is reset with the value in the WDOGMVRP system register WDOGREFRESH 0x0C W N A Writing the value 0xAC15DE42 to this register causes the counter to be updated with the value in the WDOGLOAD register WDOGENABLE 0x10 R WDOGENABLE Watchdog timer enables register This register is reset with the value in the WDOGENABLE bit in the WDOG_CR system register WDOGCONTROL 0x14 R W 31 3 and ...

Page 673: ...s register is written to while the current value of the counter is greater than the value in the WDOGMVRP register the counter is refreshed and a reset or timeout interrupt is generated depending on the MODE bit of the WDOGCONTROL While the counter value is greater than the WDOGMVRP there is effectively a time window in which it is forbidden to refresh the watchdog timer When the counter is in bet...

Page 674: ...T interrupt generation is disabled 1 The WDOGTIMEOUTINT interrupt generation is enabled Table 642 WDOGSTATUS Bit Number Name Reset Value Description 31 1 Reserved 0 To provide the compatibility to the future products the value of a reserved bit should be preserved across a read modify write operation 0 REFRESHSTATU S 0 Refresh status 0 The counter is in forbidden window refresh should not be initi...

Page 675: ...ained in System Register Block page 670 Table 644 Watchdog Timer SYSREG Register Name Register Type Flash Write Protect Reset Source Description WDOG_CR RW P Register Poreset_n Bit 0 of this register is WDOGENABLE This goes as the Enable bit for the watchdog timer module The status of this bit can be monitored in the WDOGENABLE register Bit 1of this register is WDOGMODE This bit is Reset Interrupt...

Page 676: ...cing of reset signals in SmartFusion2 devices It is available in the Libero System on Chip SoC IP catalog The System Builder is a powerful design tool within the Libero SoC Design Environment that helps you capture your system level requirements and produces a design implementing those requirements A very important function of the System Builder is the automatic creation of the initialization sub ...

Page 677: ...ch their threshold point VDD 0 9 V VPP 0 9 V the 1 MHz RC Oscillator is turned on which provides the clock to the programmable delay counter The delay can be configured to 50 µs 1 ms 10 ms or 100 ms in the New Project window Device Settings while creating the Libero SoC project as shown in the following figure You can also access and change this setting after the project has been created from the ...

Page 678: ...le by instantiating the SYSRESET macro from the Libero SoC IP catalog in SmartDesign or by instantiating the SYSRESET macro directly in the HDL file The following figure shows a block symbol of the SYSRESET macro that exposes the POWER_ON_RESET_N signal Figure 278 SYSRESET Macro POWER_ON_RESET_N asserts on the following events Power up event Assertion of DEVRST_N Completion of programming Completi...

Page 679: ...esign DEVRST_N is a dedicated input only reset pad available on all the SmartFusion2 devices 21 1 2 Power Up to Functional Time Sequence The following figure shows the power up to functional time sequence diagram Figure 279 Power up to Functional Time Sequence Diagram 6XSSO 5DPS 9 933 9 9 3 0 5 2VFLOODWRU 7XUQV 2Q LH 5DPS 3RZHU RQ 5HVHW HOD RQILJXUDWLRQ LEHUR 6R 3RZHU 2Q 5HVHW 32B5 6 7B1 5HOHDVHG ...

Page 680: ...ator enables the user to expose the MSS_RESET_N_M2F signal to the fabric Refer to How to Use the Reset Controller page 666 for more information In order to simplify the task of initializing a user design in SmartFusion2 devices Microsemi provides a CoreResetP soft Reset Controller IP The CoreResetP handles sequencing of reset signals in SmartFusion2 devices The CoreResetP generates a fabric reset ...

Page 681: ...o a latch and given to an output buffer which is then connected to an input buffer of the fabric using external loopback This input is used for stopping the counter from incrementing The counter stops as soon as the counter s LSB bit transitions to logic HIGH The power up to functional time is measured from the VDD supply ramp to transition of the fabric buffer output The following figure shows th...

Page 682: ...art Point End Point Description Power Up to Functional Time µs 005 010 025 050 060 090 150 Case1 POWER_ON_R ESET_N Output available at I O Fabric to output 647 500 531 483 474 524 647 Case 2 POWER_ON_R ESET_N MSS_RESET_N _ M2F Fabric to MSS 644 497 528 480 468 518 641 Case 3 MSS_RESET_ N_M2F Output available at I O MSS to output 3 6 3 6 3 6 3 4 4 9 4 8 4 8 Case 4 VDD Output available at I O VDD at...

Page 683: ... level to input buffer weak pull 2500 2487 2509 2475 2507 2519 2617 VDD MSIO input buffer weak pull VDD at its minimum threshold level to input buffer weak pull 2504 2491 2510 2478 2517 2525 2620 VDD MSIOD input buffer weak pull VDD at its minimum threshold level to input buffer weak pull 2479 2468 2493 2458 2486 2499 2595 Table 645 VDD Power Up to Functional Time continued Test Case Start Point E...

Page 684: ...d period variability At times it is approximately equal to twice the power on reset delay setting 6XSSO 5DPS 9 933 3RZHU RQ 5HVHW 32B5 6 7B1 UHOHDVHG 0 5 2VFLOODWRU JDWHG RII DQG 0 5 RVFLOODWRU WXUQV 2Q 1R HV 32 5B21B5 6 7B1 6LJQDO 5HOHDVHG 3 DEULF 65 0 65 0 0 7 WXUQV 2Q 066 5HVHW 6 B066B5 6 7B1 5HOHDVHG OO PDQGDWRU 2 EDQN VXSSOLHV DUH SRZHUHG 0 5 RVFLOODWRU WXUQV 2Q 3RZHU RQ UHVHW GHOD FRQILJXUDW...

Page 685: ...ower up to functional time of M2S005 M2S010 M2S025 M2S050 M2S060 M2S090 and M2S150 devices with MSS clock ranging from 3 MHz to 166 MHz Note The timing numbers shown in the below table is for worst case condition Table 646 DEVRST_N Power Up to Functional Time Test Case Start Point End Point Description Power Up to Functional Time µs 005 010 025 050 060 090 150 Case1 POWER_ON_ RESET_N Output availa...

Page 686: ...215 DEVRST_N MSIO input buffer weak pull DEVRST_N to input buffer weak 208 202 197 193 216 215 215 DEVRST_N MSIOD input buffer weak pull DEVRST_N to input buffer weak 208 202 197 193 216 215 215 Table 646 DEVRST_N Power Up to Functional Time continued Test Case Start Point End Point Description Power Up to Functional Time µs 005 010 025 050 060 090 150 ...

Page 687: ...timing numbers in Table 645 page 648 and Table 646 page 651 are for worst case conditions 9567B1 3RZHU RQ 5HVHW 32B5 6 7B1 UHOHDVHG 0 5 2VFLOODWRU JDWHG RII DQG 0 5 RVFLOODWRU WXUQV 2Q 1R HV QSXW XIIHU QDEOH 3 DEULF 65 0 65 0 0 7 WXUQV 2Q 066 UHVHW 6 B066B5 6 7B1 5HOHDVHG 066 WR DEULF 5HVHW 066B5 6 7B1B0 5HOHDVHG 2XWSXW XIIHU QDEOH 2XWSXW DYDLODEOH DW 2 OO PDQGDWRU 2 EDQN VXSSOLHV DUH SRZHUHG 32 5...

Page 688: ...nal to the fabric alignment clock controller FACC 21 2 5 System Reset The system reset SYSRESET_N is generated if any of the following conditions are true SYS_RESET_REQ is asserted from Cortex M3 processor SYS_RESET_REQ from the Cortex M3 processor is controlled by the SYSRESETREQ bit in the Application Interrupt and the Reset Control register located at 0XE000ED0C For more information refer to Co...

Page 689: ...r on assertion of SYSRESET_N It also shows the reset inputs to the Reset Controller which cause the generation of SYSRESET_N Figure 287 Functional Block Diagram of Reset Controller During SYSRESET_N SYSRESET_N resets all blocks in the MSS When SYSRESET_N asserts low the entire Cortex M3 processor is reset except for the debug logic that exists in the following blocks Nested vectored interrupt cont...

Page 690: ..._M3_CLK_N 2 M3_PORESET_TCK_N 3 T_RESET_N 4 M3_SYS_RESET_N 5 M3_TRST_N The source of the Cortex M3 processor reset captured in the RESET_SOURCE_CR register defined in Table 648 page 669 The register captures the status of the resets so that once the Cortex M3 processor comes out of reset it can read this register and take further necessary action Cortex M3 processor reset signal generation is expla...

Page 691: ... Cortex M3 processor after the rest of the MSS has been released from reset This allows to perform a secure hardware based code shadowing function thereby minimizing boot time 21 2 6 1 5 M3_TRST_N This signal is originates from System Controller and drives the NTRST debug reset input of the Cortex M3 processor and is used to reset the SWJ DP sub block within the Cortex M3 processor 21 2 6 2 MDDR R...

Page 692: ... The Reset Controller drives the reset input of the Watchdog Timer 21 2 6 3 2 PO_RESET_RCOSC_N The PO_RESET_RCOSC_N is a synchronized version of the PO_RESET_N signal on CLK_RCOSC It asserts asynchronously and negates synchronously to CLK_RCOSC This is a power on reset signal to the Watchdog Timer 21 2 6 4 Clock Controller Reset 21 2 6 4 1 CC_RESET_N The CC_RESET_N is generated on the assertion of...

Page 693: ...ntire GPIO bank can be kept in reset by asserting the MSS_GPIO_SOFTRESET bit in SOFT_RESET_CR defined in Table 648 page 669 of SYSREG A particular GPIO byte can be reset by asserting the corresponding MSS_GPIO_xx_xx_SOFTRESET bit in SOFT_RESET_CR defined in Table 648 page 669 of SYSREG The generation of GPOUT bank resets for flash bit control is shown in the following figure Only one GPOUT byte ba...

Page 694: ...following Reset sub systems in SmartFusion2 devices that must be sequenced properly for the overall system to function correctly Chip Boot System Controller Fabric MSS Cortex M3 processor FIC sub systems MSS to Fabric and Fabric to MSS Peripherals MDDR FDDR and SERDESIF CoreResetP Soft Reset Controller gathers various reset signals from system controller MSS and FPGA fabric and generates new synch...

Page 695: ...doing any transaction the MSS should be ready The following figure shows the typical FIC subsystem with CoreResetP connectivity CoreResetP generates MSS_READY signal which indicates that MSS is ready for communication MSS_READY signal is generated whenever a cold reset power up event or assertion of DEVRST_N occurs or due to MSS reset e g watchdog timeout event assertion of MSS_RESET_N_F2M etc Cor...

Page 696: ... the CoreResetP generates SDIFx_PHY_RESET_N and SDIFx_CORE_RESET_N signals which need to be connected to SERDES_IF macro on PHY_RESET_N and CORE_RESET_N respectively For FDDR and MDDR the CoreResetP generates CORE reset signals FDDR_CORE_RESET_N and MDDR_DDR_AXI_S_CORE_RESET_N Figure 297 CoreResetP Connectivity with Peripheral Resets 0 5B 5B B6B 25 B5 6 7B1 RUH5HVHW3 6 B 25 B5 6 7B1 6 B3 B5 6 7B1 ...

Page 697: ... Figure 298 CoreResetP Connectivity with SERDES_IF Block 21 3 2 Implementation If the System Builder tool is used within the Libero SoC software to construct a design targeted at a SmartFusion2 device CoreResetP will automatically be instantiated and connected within the design if required You can manually instantiate and configure CoreResetP within a SmartDesign design if required Refer to the Co...

Page 698: ... by the Assertion of POWER_N_RESET_N Figure 300 Timing for Reset Signals Initiated by the Assertion of FIC_2_APB_M_PRESET_N 32 5B21B5 6 7B1 B5 6 7B1 86 5B B5 6 7B1 5 6 7B1B 0 0 B5 6 7B1 7B5 6 7B287 0 5B 5B B6B 25 B5 6 7B1 5B 25 B5 6 7B1 3 B 2 6 B63 B 2 6 B3 B5 6 7B1 6 B 25 B5 6 7B1 1 7B 21 21 B 21 XV 5 VHWWOLQJ WLPH B B 3 B0B35 6 7B1 B5 6 7B1 86 5B B5 6 7B1 5 6 7B1B 0 0 B5 6 7B1 7B5 6 7B287 0 5B 5...

Page 699: ...ER_FAB_RESET_IN_N 7B5 6 7B 1B1 B5 6 7B1 86 5B B5 6 7B1 5 6 7B1B 0 0 B5 6 7B1 7B5 6 7B287 0 5B 5B B6B 25 B5 6 7B1 5B 25 B5 6 7B1 3 B 2 6 B63 B 2 6 B3 B5 6 7B1 6 B 25 B5 6 7B1 1 7B 21 21 B 21 XV 5 VHWWOLQJ WLPH 86 5B B5 6 7B 1B1 B5 6 7B1 86 5B B5 6 7B1 5 6 7B1B 0 0 B5 6 7B1 7B5 6 7B287 0 5B 5B B6B 25 B5 6 7B1 5B 25 B5 6 7B1 3 B 2 6 B63 B 2 6 B3 B5 6 7B1 6 B 25 B5 6 7B1 1 7B 21 21 B 21 XV 5 VHWWOLQJ ...

Page 700: ...Libero SoC project as shown in the following figure Users can also access and change this setting after the project has been created from the Project Settings window Figure 303 Ramp Delay Configuration 21 4 2 Reset Controller Configurator The resets MSS_RESET_N_F2M M3_RESET_N and MSS_RESET_N_M2F can be enabled using the Reset Controller configurator in Libero SoC as shown in the following figure F...

Page 701: ...he fabric logic to M3_RESET_N 5 Instantiate the fabric CCC and SYSRESET_N for driving the clock and reset to fabric logic 6 Connect the fabric logic to M3_RESET_N and make the other connections as shown in the following figure MSS_RESET_N_F2M is promoted to the top level for resetting the MSS from an external switch Figure 306 Connecting Fabric Logic 21 4 2 2 Use Model 2 Creating Initialization Su...

Page 702: ...creating Initialization Sub system using the System Builder CoreResetP SYSRESET and Oscillator are Instantiated and connections are made automatically 1 Select Use System Builder while creating a new project from the Design Templates and Creators panel in Libero SoC 2 System builder Device Features GUI is pop up Click Next 3 Drag Fabric AMBA Slave core from Fabric Slave Cores panel into MSS FIC_0 ...

Page 703: ...sh Write Protect Reset Source Description GPIO_SYSRESET_SEL_CR RW P Register PORESET_N Configures the GPIO system reset SOFT_RESET_CR RW P Bit SYSRESET_N Generates the software control resets to the MSS peripherals RESET_SOURCE_CR RW Reset source control register The source of Cortex M3 processor reset is captured in this register The reset values are mentioned in the bit definitions MDDR_CR RW P ...

Page 704: ...Write protect bits are flash configuration bits that are set based on user inputs to the MSS configurator These bits are defined during the device design phase and can only be modified by reprogramming the device Users have the ability to set protection levels for the entire register independent fields within each register or individual bits within each register 22 0 1 1 Register Write Protect One...

Page 705: ...a Bit Write Protect bit allocated for each bit within the register Figure 311 Bit Write Protect Refer to the Register Lock Bits Configuration page 674 for locking and unlocking registers 22 0 2 Register Types There are several register types in the SYSREG block as defined in the following table Table 649 Register Types Type Function RW P Supports read and write accesses via AHB bus matrix Refer to...

Page 706: ...O U Does not support read or write access via AHB bus matrix Refer to Figure 316 page 674 Register contents are initialized from flash configuration bits at power up and the assertion of SYS_RESET_N Typically used for MSS Control Registers RO P Supports read only accesses via AHB bus matrix Refer to Figure 315 page 674 Register contents are initialized from flash configuration bits at power up and...

Page 707: ...331 User Guide Revision 15 0 673 Figure 313 RW Type Figure 314 RO Type R Q D S SYSRESENT_N REG_BIT Reset Controller MSS Hardware Default per bit RDATA n 1 0 WDATA n AHB Bus Matrix WRITE LOADENABLEFLOP MSS RDATA n AHB Bus Matrix ...

Page 708: ...ck bits are set in a text txt file which is then imported into the SmartFusion2 project From the Design Flow window click Configure Register Lock Bits to open the configurator Then click Browse to navigate to the text file txt that contains the Register Lock Bit settings see the following figure Figure 317 Register Lock Bit Settings R Q D S Flash Configuration Bit SYSRESET_N REG_BIT MSS_P per bit ...

Page 709: ... Lock bits syntax for a register Physical block name _ register name _LOCK Lock bits syntax for a specific field Physical block name _ register name _ field name _LOCK The following are the physical block names varies with device family and die MSS FDDR SERDES_IF_x where x is 0 1 2 3 to indicate the physical SERDES location for SmartFusion2 M2S010 025 050 150 devices SERDES_IF2 for SmartFusion2 M2...

Page 710: ...r SYSRESET_ N Controls address mapping of the eSRAMs ESRAM_MAX_LAT 0x4 RW P Register SYSRESET_ N eSRAM0 and eSRAM1 maximum latency DDR_CR 0x8 RW P Register SYSRESET_ N DDR Configuration Register ENVM_CR 0XC RW P Register SYSRESET_ N eNVM Configuration Register ENVM_REMAP_BASE_CR 0x10 RW P Register SYSRESET_ N eNVM Remap Base Address Control Register ENVM_REMAP_FAB_CR 0x14 RW P Register SYSRESET_ N...

Page 711: ...rol Register MDDR_CR 0x60 RW P Register PORESET_N MDDR Configuration Register USB_IO_INPUT_SEL_CR 0x64 RW P Register PORESET_N Configures USB data interfaces from IOMUXCELLs and I O pads PERIPH_CLK_MUX_SEL_CR 0x68 RW P Register PORESET_N Peripheral Clock MUX Select Control Register WDOG_CR 0x6C RW P Register PORESET_N Configures Watchdog timer MDDR_IO_CALIB_CR 0x70 RW P Register PORESET_N MDDR I O...

Page 712: ...SRESET_ N MAC status clear on read RESET_SOURCE_CR 0xB0 RW Reset Source Control Register CC_DC_ERR_ADDR_SR 0xB4 RO SYSRESET_ N Dcode Bus Error Address Status Register CC_IC_ERR_ADDR_SR 0xB8 RO SYSRESET_ N Icode Bus Error Address Status Register CC_SB_ERR_ADDR_SR 0xBC RO SYSRESET_ N System Bus Error Address Status Register Reserved 0xC0 SYSRESET_ N CC_IC_MISS_CNTR_SR 0xC4 RO SYSRESET_ N ICode Miss ...

Page 713: ...ET_ N 1 bit error and 2 bit error count of USB CAN_EDAC_CNT 0x108 RO SYSRESET_ N 1 bit error and 2 bit error count of CAN ESRAM0_EDAC_ADR 0x10C RO SYSRESET_ N Address from eSRAM0 on which 1 bit and 2 bit SECDED error has occurred ESRAM1_EDAC_ADR 0x110 RO SYSRESET_ N Address from eSRAM1 on which 1 bit and 2 bit SECDED error has occurred MAC_EDAC_RX_ADR 0x114 RO SYSRESET_ N Address from MAC receiver...

Page 714: ... Register ENVM_PROTECT_USER 0x144 RO U SYSRESET_ N Configuration for accessibility of protect regions of eNVM0 and eNVM1 ENVM_STATUS 0x148 RO U PORESET_N Code shadow Status Register DEVICE_VERSION 0x14C RO Configures device version MSSDDR_PLL_STATUS 0x150 RO MSS DDR PLL Status Register USB_SR 0x154 RO SYSRESET_ N USB Status Register ENVM_SR 0x158 RO SYSRESET_ N Busy status eNVM0 and eNVM1 Reserved...

Page 715: ...r eSRAM0 eSRAM1 MAC USB and CAN MSS_INTERNAL_SR 0x194 SW1C SYSRESET_ N MSS Internal Status Register MSS_EXTERNAL_SR 0x198 SW1C SYSRESET_ N MSS External Status Register WDOGTIMEOUTEVENT 0x19C SW1C PORESET_N Watchdog Time out event register CLR_MSS_COUNTERS 0x1A0 W1P SYSRESET_ N Clear MSS counters CLR_EDAC_COUNTERS 0x1A4 W1P SYSRESET_ N Clears 16 bit counter value in eSRAM0 eSRAM1 MAC USB and CAN co...

Page 716: ...2CLOOPBACK and MSS_GPIOLOOPBACK GPIO_SYSRESET_SEL_CR MSS_GPIO_7_0_SYSRESET_SEL MSS_GPIO_15_8_SYSRESET_SEL MSS_GPIO_23_16_SYSRESET_SEL and MSS_GPIO_31_24_SYSRESET_SEL GPIN_SRC_SEL_CR MSS_GPINSOURCE MDDR_CR MDDR_CONFIG_LOCAL SDR_MODE F_AXI_AHB_MODE and PHY_SELF_REF_EN USB_IO_INPUT_SEL_CR USB_IO_INPUT_SEL PERIPH_CLK_MUX_SEL_CR SPI0_SCK_FAB_SEL SPI1_SCK_FAB_SEL and TRACECLK_DIV2_SEL WDOG_CR WDOGENABLE...

Page 717: ...SW_CC_ESRAM1FWREMAP is 0 then eSRAM_0 is at location 0x00000000 and eSRAM_1 is always remapped to be just above eSRAM_0 the two eSRAMs are adjacent in ICODE DCODE space Both eSRAMs also remain visible in SYSTEM space of the Cortex M3 processor and remain visible at this location to all other non Cortex M3 processor masters The bit definitions 0 No eSRAM remap is enabled This means that eNVM or MDD...

Page 718: ... space of the Cortex M3 processor and remain visible at this location to all other non Cortex M3 processor masters The bit definitions 0 No DDR space remap is enabled This means that eNVM is present at location 0x00000000 1 DDR_Space0 and DDR_Space1 are remapped to location 0x00000000 of Cortex M3 processor ICODE DCODE space Table 656 ENVM_CR Bit Number Name Reset Value Description 31 17 Reserved ...

Page 719: ...e Read 6 All other modes Page program and Page verify 3 0110 Page Read 7 All other modes Page program and Page verify 3 0111 Page Read 8 All other modes Page program and Page verify 4 1000 Page Read 9 All other modes Page program and Page verify 4 1001 Page Read 10 All other modes Page program and Page verify 4 1010 Page Read 11 All other modes Page program and Page verify 5 1011 Page Read 12 All ...

Page 720: ...ame Reset Value Description 31 19 Reserved 0 18 1 SW_ENVMREMAPBASE 0 Offset within eNVM address space of the base address of the segment in eNVM which is to be remapped to location 0x00000000 If an eNVM protected region is defined to be read accessible by the Cortex M3 then it is read accessible by Cortex M3 at both physical and re mapped addresses However if a protected region is defined as write...

Page 721: ...if the SW_ENVMREMAPSIZE 4 0 is 01111 this corresponds to a segment size of 64KB 64KB is 2 to the power of 16 Therefore the value of N in this case is 16 So the base address of the region in this case is specified by SW_ENVMREMAPSIZE 18 16 This register should only be written by Cortex M3 processor firmware using 32 bit accesses The behavior of the system is undefined if other size accesses are use...

Page 722: ...ed 0 3 0 CC_CACHE_REGION 0 Defines the cache region size The bits have the following definitions Bit 0 First lower slot of 128 MB 0 128 MB Bit 1 Second slot of 128 MB 128 256 MB Bit 2 Third slot of 128 MB 25 384 MB Bit 3 Fourth upper slot of 128 MB 384 512 MB Table 662 CC_LOCK_BASE_ADDR_CR Bit Number Name Reset Value Description 31 19 Reserved 0 18 0 CC_LOCK_BASEADD 0 If Cache Lock mode is enabled...

Page 723: ...er is common for all buffers The value in this register will be in terms of number of M3_CLK clocks Table 665 DDRB_NB_ADDR_CR Bit Number Name Reset Value Description 31 16 Reserved 0 15 0 DDRB_NB_ADDR 0xA000 Base address of a non bufferable address region Bits 15 N 1 of this signal are compared with AHB address 31 N 15 to check whether address is in non bufferable region The value of N depends on ...

Page 724: ... DDR_DS_MAP 0 Sets the DSG master to DDR address space mapping mode 0 15 7 DDRB_BUF_SZ 0x1 Configures the write buffer and read buffer size as per DDR burst size This port is common for all buffers IDC read buffer has fixed size of 32 bytes Other buffers can be configured to 16 byte or 32 byte size 0 Buffer size is configured to 16 bytes 1 Buffer size is configured to 32 bytes 6 DDRB_IDC_EN 0x1 Al...

Page 725: ...DAC_EN 0 Allows the EDAC for CAN to be disabled Allowed values 0 Disabled 1 Enabled 5 USB_EDAC_EN 0 Allows the EDAC for USB to be disabled Allowed values 0 Disabled 1 Enabled 4 MAC_EDAC_RX_EN 0 Allows the EDAC for Ethernet Rx RAM to be disabled Allowed values 0 Disabled 1 Enabled 3 MAC_EDAC_TX_EN 0 Allows the EDAC for Ethernet Tx RAM to be disabled Allowed values 0 Disabled 1 Enabled 2 Reserved 0 ...

Page 726: ...master It is configurable from 1 to 32 32 by default 9 5 SW_WEIGHT_S 0 Configures the round robin weight for S master It is configurable from 1 to 32 32 by default 4 0 SW_WEIGHT_IC 0 Configures the round robin weight for IC master It is configurable from 1 to 32 32 by default Table 671 MASTER_WEIGHT1_CR Bit Number Name Reset Value Description 31 15 Reserved 0 14 10 SW_WEIGHT_G 0 Configures the rou...

Page 727: ...O_OUT 23 16 in reset 22 MSS_GPOUT_15_8_SOFTRESET 0x1 0 Releases GPIO_OUT 15 8 from reset 1 Keeps GPIO_OUT 15 8 in reset 21 MSS_GPOUT_7_0_SOFTRESET 0x1 0 Releases GPIO_OUT 7 0 from reset 1 Keeps GPIO_OUT 7 0 in reset 20 MSS_GPIO_SOFTRESET 0x1 0 Releases the GPIO from reset as long as it isn t being held in reset by some other means 1 Keeps the GPIO to be held in reset Asserting this soft reset bit ...

Page 728: ... 8 MMUART1_SOFTRESET 0x1 0 Releases MMUART_1 from reset 1 Keeps MMUART_1 in reset 7 MMUART0_SOFTRESET 0x1 0 Releases MMUART_0 from reset 1 Keeps MMUART_0 in reset 6 TIMER_SOFTRESET 0x1 0 Releases the system timer from reset 1 Keeps the system timer in reset 5 PDMA_SOFTRESET 0x1 0 Releases the PDMA from reset 1 Keeps the PDMA in reset 4 MAC_SOFTRESET 0x1 0 Releases the Ethernet MAC from reset 1 Kee...

Page 729: ...ows STCALIB 25 NOREF bit of SysTick Calibration Value Register 1 indicates STCLK is not provided STCALIB 24 SKEW bit of SysTick Calibration Value Register 1 indicates calibration value is not exactly 10 ms STCALIB 23 0 TENMS field of SysTick Calibration Value Register reload value to use for 10 ms timing Table 676 FAB_IF_CR Bit Number Name Reset Value Description 31 10 Reserved 0 9 4 SW_FIC_REG_SE...

Page 730: ...nal loopback on the MSS GPIO is enabled Allowed values 0 No internal loopback 1 MSS GPIO outputs are looped back to MSS GPIO inputs 2 MSS_I2CLOOPBACK 0 Controls whether internal loopback between I2C_0 and I2C_1 is enabled Allowed values 0 No internal loopback 1 Traffic from I2C_0 is looped back to I2C_ and vice versa 1 MSS_SPILOOPBACK 0 Controls whether internal loopback between SPI_0 and SPI_1 is...

Page 731: ..._SEL 0 0 Selects the combination of either power on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1 Causes GPIO 7 0 to be held in reset by the soft reset signal MSS_GPIO_7_0_SOFT_RESET Table 679 GPIN_SRC_SEL_CR Bit Number Name Reset Value Description 31 0 MSS_GPINSOURCE 0 Used as select signal to generate a GPIO input signal by selecting two output signals from differ...

Page 732: ...it Number Name Reset Value Description 31 2 Reserved 0 1 0 USB_IO_INPUT_SEL 0 Selects one of the four USB data interfaces from IOMUXCELLs and I O pads Depending on the device and package not all interfaces may be available Allowed values 00 USBA interface can be connected to USB 01 USBB interface can be connected to USB 10 USBC interface can be connected to USB 11 USBD interface can be connected t...

Page 733: ...MDDR_IO_CALIB_CR Bit Number Name Reset Value Description 31 15 Reserved 0 14 CALIB_LOCK 0 Used in the DDRIO calibration block as an override to lock the codes during intermediate runs When the firmware receives CALIB_INTRPT it may choose to assert this signal by prior knowledge of the traffic without going through the process of putting the DDR into self refresh This bit is only read write 13 CALI...

Page 734: ...N 0 Allows the 2 bit error EDAC for Ethernet Rx RAM status update to be disabled Allowed values 0 Disabled 1 Enabled 8 MAC_EDAC_RX_1E_EN 0 Allows the 1 bit error EDAC for Ethernet Rx RAM status update to be disabled Allowed values 0 Disabled 1 Enabled 7 MAC_EDAC_TX_2E_EN 0 Allows the 2 bit error EDAC for Ethernet Tx RAM status update to be disabled Allowed values 0 Disabled 1 Enabled 6 MAC_EDAC_TX...

Page 735: ...d Table 686 USB_CR Bit Number Name Reset Value Description 31 2 Reserved 0 1 USB_DDR_SELECT 0 Used to configure USB works in single data rate SDR mode or double data rate DDR mode Allowed values 0 SDR mode is selected 1 DDR mode is selected 0 USB_UTMI_SEL 0 Used to configure the USB interface as ULPI PHY or UTMI interface Allowed values 0 ULPI PHY interface is selected 1 UTMI interface is selected...

Page 736: ...sk the cache interrupt to the Cortex M3 processor 6 0 SW_INTERRUPT_EN 0x7F Used to mask the AHB bus interrupt to the Cortex M3 processor Table 689 RTC_WAKEUP_CR Bit Number Name Reset Value Description 31 3 Reserved 0 2 RTC_WAKEUP_C_EN 0 Enables RTC_WAKEUP interrupt to the system controller 1 RTC_WAKEUP_FAB_EN 0 Enables the RTC_WAKEUP interrupt to the fabric 0 RTC_WAKEUP_M3_EN 0 Enables the RTC_WAK...

Page 737: ...pm 101 16000 ppm 010 2000 ppm 110 32000 ppm 011 4000 ppm 111 64000 ppm 22 19 FACC_PLL_RANGE 0 Configures the MPLL filter range The bit definitions are in Table 692 page 704 19 16 FACC_PLL_DIVQ 0x2 Configures the MPLL output divider value in order to generate the DDR clock Output divider values are given by 000 Divided by 1 001 Divided by 2 010 Divided by 4 011 Divided by 8 100 Divided by 16 101 Di...

Page 738: ... for the MPLL 7 6 FACC_PLL_SSMD 0 Drives the spread spectrum modulation depth SSMD input of the MPLL The only allowable value to be programmed in this field is 0 as spread spectrum mode is not supported for the MPLL 5 FACC_PLL_SSE 0 Drives the SSE input of the MPLL The only allowable value to be programmed in this field is 0 as spread spectrum mode is not supported for the MPLL 4 FACC_PLL_PD 0 A P...

Page 739: ...ontroller which then waits for the MPLL to come into lock before clearing this bit and thereby selecting the MPLL output as the MSS clock source again The allowed values of this bit are 0 The corresponding FACC multiplexer select lines or clock gate control line co mes from the normal run time configuration signals from relevant MSS system register bits 1 The corresponding FACC multiplexer select ...

Page 740: ...DIVISOR 0 Indicates the ratio between CLK_A and the clock being used in the fabric to clock the soft IP block which is interfacing to FIC_0 of the MSS The user can write to this field dynamically during run time even when the source clock is active The allowed ratios for CLK_A fabric clock FIC_0 are listed in Table 695 page 707 12 FACC_GLMUX_SEL 0 Contains the select line for the four no glitch mu...

Page 741: ...his field statically Do not write to this field while the source clock is active Table 695 Clock Ratio Bits Clock Ratio 000 1 1 001 2 1 010 4 1 100 8 1 101 16 1 110 32 1 Other values Reserved Table 696 MSSDDR_FACC2_CR Bit Number Name Reset Value Description 31 14 Reserved 0 13 MSS_XTAL_RTC_EN 0x1 Enable signal for auxiliary crystal oscillator RTC crystal oscillator 12 MSS_XTAL_EN 0x1 Enables the s...

Page 742: ...s 0 MUX 1 output comes from RCOSC_1MHZ Bit 8 feeds into the second rank 2 to 1 MUX Standby MUX 2 and is defined as follows 0 MUX 2 output comes from MUX 0 1 MUX 2 output comes from MUX 1 Do not write to this field while the standby clock is active 5 FACC_PRE_SRC_SEL 0 Must always be 0 Allowed values 0 RCOSC_1MHZ is fed through to the source no glitch clock multiplexer 4 2 FACC_SRC_SEL 0 Contains t...

Page 743: ...essor 2 FAB_PLL_LOCK_EN 0 Masking signal to enable Fabric PLL LOCK interrupt to Cortex M3 processor 1 MPLL_LOCK_LOST_EN 0 Masking signal to enable MPLL LOCK LOST interrupt to Cortex M3 processor 0 MPLL_LOCK_EN 0 Masking signal to enable MPLL LOCK interrupt to Cortex M3 processor Table 698 MSSDDR_CLK_CALIB_CR Bit Number Name Reset Value Description 31 1 Reserved 0 0 FAB_CALIB_START 0 Writing to thi...

Page 744: ...xt reset event Reset signal WDOGTIMEOUT_M3_CLK_N 4 LOCKUP_RESET_DETECT 0x1 Indicates that a Cortex M3 processor lockup reset has occurred During the device boot sequence this register should be cleared to arm it to detect the next reset event The reset signal for this bit is LOCKUP_DEL2_N 3 SOFT_RESET_DETECT 0x1 Indicates that a soft reset has occurred During the device boot sequence this register...

Page 745: ...s on which an error has occurred Table 704 CC_SB_ERR_ADDR_SR Bit Number Name Reset Value Description 31 0 CC_SB_ERR_ADDR 0 Stores the address from the system bus on which an error has occurred Table 705 CC_IC_MISS_CNTR_SR Bit Number Name Reset Value Description 31 0 CC_IC_MISS_CNT 0 Counts the total number of cache misses that occurs on the cacheable region through the ICode bus Rolls back after m...

Page 746: ...iption 31 0 CC_DC_HIT_CNT 0 Counts the total number of cache hits that occurs on the cacheable region through the DCode bus Rolls back after maximum value This counter is put to reset value by setting CC_DC_HIT_CNTCLR Table 709 CC_IC_TRANS_CNTR_SR Bit Number Name Reset Value Description 31 0 CC_IC_TRANS_CNT 0 Keeps count of the total number of transaction counts processed by the cache engine cache...

Page 747: ...DRB_HPD_ERR_ADD 0 If a write transfer initiated at the MSS DDR bridge arbiter interface to empty data present in the write buffer of the HPDMA master which receives an error response the address for which the error response is received is placed in this register Address indicates TAG value for which error response is received The following values are updated in this register as per buffer size 16 ...

Page 748: ...RB_DS_WBEMPTY 0 When set to 1 indicates that the write buffer of the DSG master does not have valid data Table 715 DDRB_DSBL_DN_SR Bit Number Name Reset Value Description 31 7 Reserved 0 6 DDRB_IDC_DSBL_DN 0 Is set to 1 once the AHB bus matrix read buffer is disabled after getting a read buffer disable command from processor 5 DDRB_HPD_RDSBL_DN 0 Is set to 1 once the HPDMA read buffer is disabled ...

Page 749: ...mum value 15 0 ESRAM1_EDAC_CNT_1E 0 16 bit counter value in eSRAM1 incremented by eSRAM1 EDAC 1 bit error The counter will not roll back and will stay at its maximum value Table 718 MAC_EDAC_TX_CNT Bit Number Name Reset Value Description 31 16 MAC_EDAC_TX_CNT_2E 0 16 bit counter that counts the number of 2 bit errors for Ethernet MAC TX EDAC The counter will not roll back and will stay at its maxi...

Page 750: ...t counter that counts the number of 2 bit errors for CAN The counter will not roll back and will stay at its maximum value 15 0 CAN_EDAC_CNT_1E 0 16 bit counter that counts the number of 1 bit errors for CAN The counter will not roll back and will stay at its maximum value Table 722 ESRAM0_EDAC_ADR Bit Number Name Reset Value Description 31 26 Reserved 0 25 13 ESRAM0_EDAC_2E_AD 0 Stores the addres...

Page 751: ...Reserved 0 25 13 MAC_EDAC_TX_2E_AD 0 Stores the address from Ethernet TX memory on which a 2 bit SECDED error has occurred 12 0 MAC_EDAC_TX_1E_AD 0 Stores the address from Ethernet TX memory on which a 1 bit SECDED error has occurred Table 726 CAN_EDAC_ADR Bit Number Name Reset Value Description 31 26 Reserved 0 25 13 CAN_EDAC_2E_AD 0 Stores the address from CAN memory on which a 2 bit SECDED erro...

Page 752: ... to slave 2 4 MM0_1_2_MS2_ALLOWED_R 1 Read security bits for masters 0 1 and 2 to slave 2 eNVM0 If not set masters 0 1 and 2 will not have read access to slave 2 3 MM0_1_2_MS1_ALLOWED_W 1 Write security bits for masters 0 1 and 2 to slave 1 eSRAM1 If not set masters 0 1 and 2 will not have write access to slave 1 2 MM0_1_2_MS1_ALLOWED_R 1 Read security bits for masters 0 1 and 2 to slave 1 eSRAM1 ...

Page 753: ... 1 1 MM4_5_DDR_FIC_MS0_ALLOWED_W 1 Write security bits for masters 4 5 and DDR_FIC to slave 0 eSRAM0 If not set masters 4 5 and DDR_FIC will not have write access to slave 0 0 MM4_5_DDR_FIC_MS0_ALLOWED_R 1 Read security bits for masters 4 5 and DDR_FIC to slave 0 eSRAM0 If not set masters 4 5 and DDR_FIC will not have read access to slave 0 Table 730 MM3_6_7_8_SECURITY Bit Number Name Reset Value ...

Page 754: ...ot set master 9 will not have write access to slave 6 8 MM9_MS6_ALLOWED_R 1 Read security bits for master 9 to slave 6 MSS DDR bridge If not set master 9 will not have read access to slave 6 7 MM9_MS3_ALLOWED_W 1 Write security bits for master 9 to slave 3 eNVM1 If not set master 9 will not have write access to slave 3 6 MM9_MS3_ALLOWED_R 1 Read security bits for master 9 to slave 3 eNVM1 If not s...

Page 755: ...e 32 bit lower bits of timestamp value TSVALUEB from the Cortex M3 processor Table 734 ETM_COUNT_HIGH Bit Number Name Reset Value Description 31 28 Reserved 0 27 25 ETMINTSTAT 0 Indicates the interrupt status The following bit definitions mark the interrupt status of the current cycle 000 No status 001 Interrupt entry 010 Interrupt exit 011 Interrupt return 100 Vector fetch and stack push ETMINTST...

Page 756: ...0 Freezes the watchdog counter There is no reset signal for this bit This bit has the following meanings 0 Watchdog counter is not frozen 1 Watchdog counter is frozen not counting down 2 FF_IN_PROGRESS_SYNC 0 Indicates the FF_IN_PROGRESS STATE There is no reset signal for this bit 1 VIRGIN_PART 0x1 Indicates the device as virgin or non virgin type There is no reset signal for this bit This bit has...

Page 757: ...s who have read access can have write access to the upper protection region of eNVM0 This will be set by the user flash row bit 6 NVM0_UPPER_OTHERS_ACCESS 0x1 When set indicates that the other masters can access the upper protection region of eNVM0 5 NVM0_UPPER_FABRIC_ACCESS 0x1 When set indicates that the fabric can access the upper protection region of eNVM0 This will be set by the user flash ro...

Page 758: ...TATUS Bit Number Name Reset Value Description 31 3 Reserved 0 2 RCOSC_DIV2 Input from the System Controller indicating whether the 50 MHz RC oscillator is running at 25 MHz or 50 MHz 0 Running at 25MHz 1 Running at 50MHz 1 MPLL_LOCK 0 MPLL lock status A LOCK signal is provided to indicate that the MPLL has locked on to the incoming signal LOCK asserts High to indicate that the MPLL has achieved fr...

Page 759: ...t this signal is tied High at the fabric interface Allowed values 0 Fabric PLL is not in lock 1 Fabric PLL is in lock or CLK_BASE is not derived from a fabric PLL Table 740 USB_SR Bit Number Name Reset Value Description 31 2 Reserved 0 1 LPI_CARKIT_EN 0 Asserted when entry is made into CarKit mode and cleared on exit from CarKit mode 0 POWERDN 0 Asserted when CLK may be stopped to save power Table...

Page 760: ...DP 7 HPDMA read request to arbiter SYR_DDRB_DP 6 AXI write address channel acknowledge to DSG write request SYR_DDRB_DP 5 AXI write address channel acknowledge to AHB bus write request SYR_DDRB_DP 4 AXI write address channel acknowledge to HPDMA write request SYR_DDRB_DP 3 AXI write data channel acknowledge to DSG write request SYR_DDRB_DP 2 AXI write data channel acknowledge to AHB bus write requ...

Page 761: ...ibration circuit is failing to operate correctly This indicates incorrectly configured delay values for M3_CLK and or fabric clock in the CCC Table 745 WDOGLOAD Bit Number Name Reset Value Description 31 26 Reserved 0 25 0 WDOGLOAD 0x1800000 Contains upper 26 bits of the WDOGLOAD value register Table 746 WDOGMVRP Bit Number Name Reset Value Description 31 0 WDOGMVRP 0xFFFFFFFF Contains the WDOGMVR...

Page 762: ...EG3 0 Stores the user configuration register 3 to be read by the Cortex M3 processor Table 751 FAB_PROT_SIZE Bit Number Name Reset Value Description 31 6 Reserved 0 5 0 SW_PROTREGIONSIZE 11110 The size of the memory region inaccessible to the FPGA fabric master is determined by the value of this bus The region sizes are listed in Table 752 page 728 Table 752 Region Size Bit 0 Bit 1 Bit 2 Bit 3 Bit...

Page 763: ... 128 KB 1 0 0 0 1 256 KB 1 0 0 1 0 512 KB 1 0 0 1 1 Reserved 1 0 1 0 0 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 8 Mbytes 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved Table 753 FAB_PROT_BASE Bit Number Name Reset Value Description 31 0 SW_PROTREGIONBASE 0 The base address of the memory region inaccessible to the FPGA fabric master is determined by the value of this bus Bit 0 of this bus is defined as SW_PROT...

Page 764: ...AM memory 10 USB_EDAC_1E 0 Updated by USB when a 1 bit SECDED error has been detected and is corrected for RAM memory 9 MAC_EDAC_RX_2E 0 Updated by Ethernet when a 2 bit SECDED error has been detected for Rx RAM memory 8 MAC_EDAC_RX_1E 0 Updated by Ethernet when a 1 bit SECDED error has been detected and is corrected for Rx RAM memory 7 MAC_EDAC_TX_2E 0 Updated by Ethernet when a 2 bit SECDED erro...

Page 765: ...ndicates that the MPLL lost lock 0 MPLL_LOCK_INT 0 Indicates that a rising edge event occurred on the MPLL_LOCK signal This indicates that the MPLL came into lock Table 757 MSS_EXTERNAL_SR Bit Number Name Reset Value Description 31 19 Reserved 0 18 CC_HRESP_ERR Indicates whether any accesses to the corresponding master on the CACHE resulted in HRESP assertion by the slave to the CACHE and hence to...

Page 766: ...s Bit 1 1 AHB bus and DS are trying to access same address Bit 2 1 HPDMA and DS are trying to access same address Bit 3 1 IDC and HPDMA are trying to access same address Bit 4 1 IDC and AHB Bus are trying to access same address Bit 5 1 IDC and DS are trying to access same address 6 0 SW_ERRORSTATUS 0 Indicates whether any accesses by the corresponding master on the AHB bus resulted in either HRESP...

Page 767: ..._MISS_CNT counter is reset Table 760 CLR_EDAC_COUNTERS Bit Number Name Reset Value Description 31 14 Reserved 0 13 CAN_EDAC_CNTCLR_2E 0 Pulse generated to clear the 16 bit counter value in CAN corresponding to the count value of EDAC 2 bit errors This in turn clears the upper 16 bits of the CAN_EDAC_CNT register 12 CAN_EDAC_CNTCLR_1E 0 Pulse generated to clear the 16 bit counter value in CAN corre...

Page 768: ...NT Register 2 ESRAM1_EDAC_CNTCLR_1E 0 Pulse generated to clear the 16 bit counter value in eSRAM1 corresponding to count value of EDAC 1 bit errors This in turn clears the lower 16 bits of the eSRAM1_EDAC_CNT Register 1 ESRAM0_EDAC_CNTCLR_2E 0 Pulse generated to clear the 16 bit counter value in eSRAM0 corresponding to count value of EDAC 2bit Errors This in turn clears the upper 16 bits of eSRAM0...

Page 769: ...master in the MSS DDR bridge to be flushed Data present in the write buffer is transferred to the MSS DDR bridge write arbiter interface when this pulse is detected 0 No effect 1 Flush HPD write buffer 2 DDRB_FLSHDS 0 Allows the write buffer for the DSG master in the MSS DDR bridge to be flushed Data in the write buffer is transferred to the MSS DDR bridge write arbiter when this pulse is detected...

Page 770: ...ng to this IOMUXCELL 7 MSS_IOMUXSEL5UPPER N 0 Used to select the source of the OE port of the I O cell corresponding to this IOMUXCELL 6 4 MSS_IOMUXSEL4 N 2 0 0 Used to select the source of the output port of the I O cell corresponding to this IOMUXCELL This field definition is in Table 765 on page 737 3 MSS_IOMUXSEL3 N 0 0 Output enable of interface MSS GPIO of IOMUXCELL goes to FPGA fabric core ...

Page 771: ...e USB Controller of IOMUXCELL 0 1 1 Output of I O cell is connected to 0 1 0 0 Output of I O cell is connected to 1 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Table 765 MSS_IOMUXSEL4 N 2 0 Bit 0 Bit 1 Bit2 Function 0 0 0 Output of I O cell comes from output of interface Serial Comms of IOMUXCELL 0 0 1 Output of I O cell comes from output of interface MSS GPIO of IOMUXCELL 0 1 0 Output of I O cel...

Page 772: ...s 43 interrupts from the MSS as inputs 16 individually configurable MSS to fabric interrupt ports 16 individually configurable fabric to MSS interrupt ports The following figure depicts the connectivity of FIIC to the AHB bus matrix Figure 319 The FIIC Connection to AHB Bus Matrix AHB Bus Matrix eSRAM_0 System Controller Cache Controller S D IC ARM Cortex M3 Processor S D I MSS DDR Bridge PDMA MS6...

Page 773: ...bric Interface Interrupt Controller There are 16 circuits as shown in the following figure Each circuit corresponds to a row in the preceding figure The dedicated interrupts coming from the MSS peripherals are always connected to the 16 M2F interrupt signals Figure 321 Combinational Circuit for Mapping MSS Interrupts to a MSS_INT_M2F Every peripheral interrupt in the MSS except I2C_SMBALERT0 I2C_S...

Page 774: ...re cleared by the far end I2C device after a firmware initiated sequence of operations WDOGTIMEOUTINT is always passed straight through the block as M3_NMI F2M interrupts from the fabric are connected to the Cortex M3 processor NVIC MSS_INT_F2M 15 0 the 16 F2M interrupts from user logic in the fabric are routed directly to the Cortex M3 processor NVIC F2M interrupts are level sensitive active high...

Page 775: ...ion2 MSS component into the Libero project and configure enable disable the peripherals as per the application needs using the MSS configurator 2 Double click or right click Interrupt Management and select the configure option as shown in the following figure Figure 322 Configure FIIC in the MSS Configurator The following options are available for configuring the FIIC subsystem Use Fabric to MSS I...

Page 776: ...the application need Use Fabric to MSS Interrupt Use this option to expose the MSS_INT_F2M interrupt port MSS_INT_F2M signals are then available to be used in the design Use MSS to Fabric Interrupt Use this option to expose MSS_INT_M2F M3_NMI and COM M_BLK_INT interrupts ports These signals are then available to be used in the design Figure 323 FIIC Configurator ...

Page 777: ...example timer counter in the FPGA fabric can also be used as a source of interrupt Figure 324 Fabric to the MSS Interrupt 23 3 2 1 1 Software Design Flow The software design flow consists of enabling the interrupts and the implementation of interrupt handlers The interrupt handler executes on the occurrence of interrupts The following is a description of the software application programming interf...

Page 778: ...e Cortex M3 interrupt controller NVIC The following API is used to clear the fabric to the MSS interrupt NVIC_ClearPendingIRQ FabricIrqX_IRQn where X can be set from 0 to 15 Note Once Fabric to MSS Interrupt is asserted user logic in the fabric must keep the interrupt asserted until it is cleared by the Cortex M3 processor firmware Table 768 Interrupt Source Numbers F2M Interrupt Signal Interrupt ...

Page 779: ...ng the MSS to the Fabric interrupt The interrupt enable registers do not affect the Cortex M3 process or the NVIC these are per bit enables of the interrupt routed to the FPGA fabric It enables the MSS to fabric interrupt MSS_INT_M2F by setting the following INTERRUPT_ENABLE0 or INTERRUPT_ENABLE1 register bit band INTERRUPT_CTRL_BITBAND bit band register bit of INTERRUPT_ENABLE0 or INTERRUPT_ENABL...

Page 780: ...ND bit band register bit of INTERRUPT_REASON0 or INTERRUPT_REASON1 I2C_INT1_ENBL FAB_PLL_LOCK_INT_ENBL MMUART0_INTR_ENBL FAB_PLL_LOCKLOST_INT_ENBL MMUART1_INTR_ENBL FIC64_INT_ENBL MAC_INT_ENBL RESERVED3 24 USB_MC_INT_ENBL PDMAINTERRUPT_ENBL HPD_XFR_CMP_INT_ENBL TIMER1_INTR_ENBL TIMER2_INTR_ENBL CAN_INTR_ENBL RTC_WAKEUP_INTR_ENBL WDOGWAKEUPINT_ENBL MSSDDR_PLL_LOCKLOST_INT_ENB L ENVM_INT0_ENBL ENVM_...

Page 781: ... RESERVED6 I2C_INT1_STATUS FAB_PLL_LOCK_INT_STATUS MMUART0_INTR_STATUS FAB_PLL_LOCKLOST_INT_STATUS MMUART1_INTR_STATUS FIC64_INT_STATUS MAC_INT_STATUS RESERVED7 24 USB_MC_INT_STATUS PDMAINTERRUPT_STATUS HPD_XFR_CMP_INT_STATUS TIMER1_INTR_STATUS TIMER2_INTR_STATUS CAN_INTR_STATUS RTC_WAKEUP_INTR_STATUS WDOGWAKEUPINT_STATUS MSSDDR_PLL_LOCKLOST_INT_STATUS ENVM_INT0_STATUS ENVM_INT1_STATUS I2C_SMBALER...

Page 782: ...LED on TIM1 interrupt __attribute__ __interrupt__ void Timer1_IRQHandler void uint32_t timer1_interrupt Read Timer1 MSS to Fabric Interrupt status timer1_interrupt INTERRUPT_CTRL_BITBAND TIMER1_INTR_STATUS Delay for extending the Timer1 MSS to fabric Interrupt pulse width delay 10000 Clear TIM1 interrupt MSS_TIM1_clear_irq 23 3 2 2 2 Soft Processor in FPGA fabric If MSS peripheral interrupt source...

Page 783: ... per bit enables of the interrupt routed to the FPGA fabric The following table summarizes each of the registers covered by this chapter The base address of the FIIC block is 0x40006000 23 5 FIIC Controller Register Bit Definitions The following tables provide the bit definitions for registers in the FIIC Table 771 SmartFusion2 SoC FPGA FIIC Register Map Register Name Address Offset Register Type ...

Page 784: ...MA block to fabric 1 Enable 0 Mask 10 TIMER1_INTR_ENBL 0 TIMER1_INTR interrupt from the MSS TIMER1 block to fabric 1 Enable 0 Mask 11 TIMER2_INTR_ENBL 0 TIMER2_INTR interrupt from the MSS TIMER2 block to fabric 1 Enable 0 Mask 12 CAN_INTR_ENBL 0 CAN_INTR interrupt from the MSS CAN controller block to fabric 1 Enable 0 Mask 13 RTC_WAKEUP_INTR_ENBL 0 RTC_WAKEUP_INTR interrupt from the MSS RTC block ...

Page 785: ...SS I2C_0 block to fabric 1 Enable 0 Mask 19 I2C_SMBSUS0_ENBL 0 I2C_SMBSUS0 interrupt from the MSS I2C_0 block to fabric 1 Enable 0 Mask 20 I2C_SMBALERT1_ENBL 0 I2C_SMBALERT1 interrupt from the MSS I2C_1 block to fabric 1 Enable 0 Mask 21 I2C_SMBSUS1_ENBL 0 I2C_SMBSUS1 interrupt from the MSS I2C_1 block to fabric 1 Enable 0 Mask 22 HPD_XFR_ERR_INT_ENBL 0 HPD_XFR_ERR_INT interrupt from the MSS HPDMA...

Page 786: ...ion being issued to the system controller 25 DDRB_INTR_ENBL 0 MSS DDR bridge DDRB_INTR to fabric 1 Enable 0 Mask DDRB_INTR input indicates that any one of the following interrupts are asserted from the MSS DDR bridge DDRB_ERROR interrupts DDRB_DISABLEDONE interrupts DDRB_LOCKTIMEOUT interrupts 26 ECCINTR_ENBL 0 ECCINTR interrupt from ESRAM0 ESRAM1 the cache controller CAN MDDR and USB to fabric 1 ...

Page 787: ...E1 Bit Number Name Reset Value Description 0 Reserved 0 Reserved 1 Reserved 0 Reserved 2 Reserved 0 Reserved 3 MDDR_IO_CALIB_INT_ENBL 0 MDDR_IO_CALIB_INT interrupt from the MDDR block to fabric 1 Enable 0 Mask 4 Reserved 0 Reserved 5 FAB_PLL_LOCK_INT_ENBL 0 FAB_PLL_LOCK_INT interrupt from FAB_PLL 1 Enable 0 Mask 6 FAB_PLL_LOCKLOST_INT_ENBL 0 FAB_PLL_LOCKLOST_INT interrupt from FAB_PLL 1 Enable 0 M...

Page 788: ... 0 Set if the interrupt source for SPIINT1 is asserted and the SPIINT1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 2 I2C_INT0_STATUS 0 Set if the interrupt source for I2C_INT0 is asserted and the I2C_INT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 3 I2C_INT1_STATUS 0 Set if the interrupt source forI2C_INT1 is asserted and the I2C_INT1_ENBL interrupt enable bit in INTERRUPT_E...

Page 789: ...ABLE0 is High 15 MSSDDR_PLL_LOCKLOST_INT_STATUS 0 Set if the interrupt source for MSSDDR_PLL_LOCKLOST_INT is asserted and the MSSDDR_PLL_LOCKLOST_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 16 ENVM_INT0_STATUS 0 Set if the interrupt source for ENVM_INT0 is asserted and the ENVM_INT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 17 ENVM_INT1_STATUS 0 Set if the interrupt sou...

Page 790: ...if the interrupt source for ECCINTR is asserted and the ECCINTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 27 CACHE_ERRINTR_STATUS 0 Set if the interrupt source for CACHE_ERRINTR is asserted and the CACHE_ERRINTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High 28 SOFTINTERRUPT_STATUS 0 Set if the interrupt source for SOFTINTERRUPT is asserted and the SOFTINTERRUPT_ENBL interrupt...

Page 791: ...le Each FIC block can operate on a different clock frequency defined as a ratio of the MSS main clock M3_CLK The SmartFusion2 architecture imposes a certain number of rules related to clocking domains between the fabric interfaces and the FPGA fabric This document provides guidance on how to properly construct such systems The following figure depicts the connectivity of FIC_0 and FIC_1 to the AHB...

Page 792: ...C_1 independently from the Libero SoC MSS configurator The following configuration options are available The MSS to the FPGA fabric interface Advanced AHB Lite options The FPGA fabric Address Regions MSS Master View Table 777 Number of FICs Available for Use in Each Device Device FIC Blocks M2S005 11 1 Only FIC_0 is available M2S010 M2S025 M2S050 2 M2S060 1 M2S090 M2S150 2 AHB Bus Matrix AHB Lite ...

Page 793: ...ation in the FIC configurator provides the Use Bypass Mode option to enable or disable the address and data pipelining between FPGA fabric logic and the AHB bus matrix In some scenarios the FPGA fabric logic needs to access the MSS peripherals such as eSRAM or eNVM with very high throughput In such cases the FPGA fabric logic should be connected to the FIC using an AHB Lite interface In bypass mod...

Page 794: ...PGA fabric 24 2 3 Configure MSS Master View for the FPGA Fabric Address There are six 256 MB regions defined as FIC Regions 0 to 5 in the MSS memory map Each of these regions can be allocated to the FIC_0 or FIC_1 slave interfaces in a mutually exclusive fashion Libero SoC MSS configurator allows you to configure the Memory Regions for the FIC Interfaces By default fabric regions 0 1 and 2 are acc...

Page 795: ...Top Level View FIC_X Bridge from MSS Master to Fabric Slave Bridge from Fabric Master to MSS Slave AHB Lite Signals from AHB Bus Matrix Master Interface to FIC_X AHB Lite Signals from FIC_X to AHB Bus Matrix Slave Interface FIC_X_APB_M_PRDATA FIC_X_APB_M_PADDR FIC_X_APB_M_PREADY FIC_X_APB_M_PSEL FIC_X_APB_M_PWRITE FIC_X_APB_M_PENABLE FIC_X_APB_M_PWDATA FIC_X_APB_M_PSLVERR FIC_X_AHB_M_HRDATA FIC_X_...

Page 796: ...E Out Indicates APB write control signal to the fabric slaves FIC_X_APB_M_PENABLE Out Indicates APB enable to the fabric slave The enable signal is used to indicate the second cycle of an APB transfer FIC_X_APB_M_PWDATA 31 0 Out Indicates APB write data to the fabric slave FIC_X_APB_M_PSLVERR In Indicates error condition on an APB transfer from the fabric slave FIC_X_AHB_S_HRDATA 31 0 Out Indicate...

Page 797: ...ave can drive this signal Low to extend a transfer FIC_X_AHB_M_HWDATA 31 0 Out Indicates AHB Lite write data to the fabric slave FIC_X_AHB_M_HRDATA 31 0 In Indicates AHB Lite read data from the fabric slave FIC_X_AHB_M_HRESP In Indicates AHB Lite transfer response from the fabric slave FIC_X_AHB_M_HSIZE 1 0 Out Indicates AHB Lite transfer size to the fabric slave FIC_X_AHB_M_HTRANS 1 0 Out Indicat...

Page 798: ...er to the fabric slave for read transaction in Synchronous Pipelined mode Figure 332 AHB Lite Bus Signals from FIC to the Fabric Slave for a Read Transaction in Synchronous Pipelined Mode T1 T2 T3 T4 T5 T6 T7 T8 A A 4 00 00 00 00 10 10 10 10 FIC_X_AHB_M_HCLK FIC_X_AHB_M_HADDR 31 0 FIC_X_AHB_M_HTRANS FIC_X_AHB_M_HSIZE FIC_X_AHB_M_HWRITE FIC_X_AHB_M_HSEL FIC_X_AHB_M_HWDATA 31 0 FIC_X_AHB_M_HREADY Da...

Page 799: ... the fabric interface controller for read transactions in Bypass mode Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it Figure 334 AHB Lite Bus Signals from Fabric Master to FIC for a Read Transaction in Bypass Mode T1 T2 T3 T4 T5 T6 T7 A A 4 00 00 10 10 10 10 FIC_X_AHB_S_HCLK FIC_X_AHB_S_HADDR 31 0 FIC_X_AHB_S_HTRANS FIC_X_AHB_S_HSIZE FIC_X_AHB_...

Page 800: ...ode the user may perform byte half word and word accesses from the fabric to MSS However in APB16 mode the user can only cause a word access to occur to an MSS slave This is done by two accesses over the APB16 one of which is to write a 16 bit holding register in the case of writes or to read a 16 bit holding register in the case of reads 24 6 Fabric Interface Clocks The fabric alignment clock con...

Page 801: ...C_1 are not configured by default in the MSS configurator when the Libero SoC project is created To configure create a FIC subsystem 1 The MSS FIC has to be configured to expose the FIC interface 2 The FPGA fabric FIC subsystem has to be created including instantiation configuration connectivity for APB or AHB Lite bus APB and AHB Lite compliant master and or peripherals configuration and connecti...

Page 802: ...is configured Figure 338 FIC Configurator 24 7 1 1 1 MSS to the FPGA Fabric Interface Interface Type Use this option to select between the AMBA APB AHB to APB bridge and AHB Lite AHB to AHB bridge FIC modes as shown in the following figure Use Master Interface Use this option to expose the Master Bus Interface BIF port When selected the port is automatically available on the MSS core Use Slave Int...

Page 803: ...ing figure Figure 341 FPGA Fabric Address Regions MSS Master View Note This option is available in FIC_0 configurator only If memory regions are required to be configured to FIC_1 the FIC_0 configurator needs to be opened 24 7 1 2 Step 2 Create the FPGA Fabric FIC Subsystem For each FIC interface master and slave exposed a bus CoreAHBLite or CoreAPB3 must be instantiated that matches the type sele...

Page 804: ...ubsystem where you have a master in the fabric that requires the remap feature and thus needs to be connected to M0 If you have selected the 16 MB per slot option there are no restrictions on which slots can be used If you have selected the 256 MB per slot option only the slots compatible with the FIC instance fabric memory address regions selection can be used Each FIC memory address region is 25...

Page 805: ...ric peripherals to the MSS FIC interfaces through the CoreAHBLite bus and CoreAPB3 bus Manual Connection Connect the CoreAHBLite mirrored master bus interface BIF port M1 to the MSS master BIF port FIC_0 1_AHB_MASTER as shown in the following figure Connect the AHB Lite slaves to the proper slots as per your memory map requirement Clocks and resets refer to the Configuring the FIC Subsystem Clocks...

Page 806: ...Fabric Interface Controller UG0331 User Guide Revision 15 0 772 Figure 345 FIC Master AHB Lite Subsystem ...

Page 807: ... in the following figure Figure 347 Master APB Slave Slots Configuration 3 Instantiate and configure APB compliant peripheral cores and or custom APB compliant components 4 Connect the subsystem together this can be done in two ways Automatic Connection Right click in the top level SmartDesign canvas and select the Auto Con nect option This connects the FPGA fabric peripherals to the MSS FIC inter...

Page 808: ...uring the FIC Subsystem Clocks To create the proper clock configuration and connectivity you must Configure the MSS CCC FIC clocks Instantiate and configure an FPGA fabric CCC core Connect the clock networks for each FIC subsystem Connect the MSS CLK_BASE port to the correct FPGA fabric FIC subsystem clock network ...

Page 809: ...rticular subsystem in the MSS_CCC configurator All the FPGA fabric FIC subsystem clocks must be precisely aligned the clocks may be of different frequencies but the rising edges of the slower clocks must be aligned to the rising edges of the fastest clocks The FPGA fabric FIC subsystem clock with the smallest frequency must drive the MSS CLK_BASE If a fabric PLL is used then the fabric PLL s LOCK ...

Page 810: ...FIC block FIC_0 and FIC_1 used in your design select the clock divisors in the MSS clock configurator MSS_CCC as shown in the following figure Figure 350 MSS CCC FIC Clock Configuration Note that the CLK_BASE field is non editable CLK_BASE frequency as imposed by the SmartFusion2 architecture must be the minimum frequency of all FIC clock frequencies and is automatically computed by the MSS CCC co...

Page 811: ...ts from a fabric PLL to guarantee the phase alignment as shown in Figure 351 page 777 Note If two FIC subsystems have the same frequencies one fabric CCC global output is sufficient for clocking both the FIC subsystems Figure 351 Fabric Clocks Configuration 24 7 2 3 Step 3 Connect the FPGA Fabric FIC Subsystems Clock Networks Connect the configured fabric CCC global outputs GLx to the associated F...

Page 812: ...figurator M3_CLK may need to be changed or clock ratio between M3_CLK and the FIC clocks increased to get a design that passes the static timing analysis 24 7 3 Configuring the FIC Subsystem Reset To configure the FIC Subsystem reset 1 Configure the MSS Reset sub block to expose the MSS_RESET_N_M2F port as shown in the following figure Figure 352 Configure the MSS Reset Sub Block 2 Connect the MSS...

Page 813: ...ugh FIC_0 or FIC_1 CoreAHBLite gives the HREADY and HSEL signals connectivity to the fabric AHB Lite slaves The MSS master AHB Lite interface passes all incoming AHB Lite transactions to the fabric with no error checking If an error has occurred during the transfer the fabric AHB Lite slaves must signal the error condition to the master so that it is aware the transfer has been unsuccessful Figure...

Page 814: ...EL connectivity to the fabric APB slaves Figure 354 APB Slaves in the FPGA Fabric Connected to the MSS The following application note describes this Use Model with a design example AC392 SmartFusion2 SoC FPGA SRAM Initialization from eNVM The design example describes a method of initializing the fabric SRAM blocks after power up with the initialization data from eNVM block using the Cortex M3 proc...

Page 815: ...ith the MSS Slave and the Fabric Master The following application note describes this Use Model with a design example AC388 SmartFusion2 SoC FPGA Dynamic Configuration of AHB Bus Matrix The design example consists of two AHB masters in FPGA fabric that write 32 bit data to the AHB bus matrix slave eSRAM1 CoreAHBLite AHB Lite Slave 1 AHB Lite Slave 15 AHB Lite Master FPGA Fabric S0 S1 S15 M0 MSS AH...

Page 816: ...ustom logic Building an APB3 Core for SmartFusion cSoC FPGAs Application Note This document describes how to create an APB wrapper interface for the user logic or IP TU0310 Interfacing User Logic with the Microcontroller Subsystem Tutorial This tutorial shows you how to interface and handle communication between the user logic in the FPGA fabric and the MSS It also explains the Libero SoC design s...

Page 817: ...m the SYSREG block Table 782 FAB_IF Register in the SYSREG Block Register name Register Type Flash Write Protect Reset Source Description FAB_IF_CR RW P Register SYSRESET_N Control register for fabric interface SOFT_RESET_CR RW P Bit SYSRESET_N Generates software control interrupts to the MSS peripherals MSSDDR_FACC1_CR RW P Field CC_SYSRESET_N MSS DDR fabric alignment clock controller 1 configura...

Page 818: ...shows the APB configuration interfaces and SERDES and DDR subsystems connectivity with the MSS master The AHB bus matrix FIC_2 port routes the APB configuration interface to the FPGA fabric The SERDES and DDR subsystems are connected through CoreSF2Config soft IP CoreSF2Config must be instantiated available in the Libero SoC IP Catalog in the FPGA fabric to allow configuration of FDDR SERDESIF and...

Page 819: ...2 Port List Table 783 FDDR APB Slave Configuration Interface Port List Port Name Direction Polarity Description APB_S_PSEL In High Indicates APB slave select APB_S_PENABLE In High Indicates APB enable APB_S_PWRITE In High APB write control signal Indicates read when Low and write when High APB_S_PADDR 10 2 In Indicates APB address Addresses are word aligned APB_S_PWDATA 15 0 In Indicates APB write...

Page 820: ...ol signal Indicates read when Low and write when High APB_S_PADDR 13 2 In Indicates APB address Addresses are word aligned APB_S_PWDATA 31 0 In Indicates APB write data APB_S_PRDATA 31 0 Out Indicates APB read data APB_S_PREADY Out Indicates APB PREADY signal and used to extend an APB transfer APB_S_PSLVERR Out High Indicates a transfer failure APB_S_PCLK In Indicates APB clock APB_S_PRESET_N In L...

Page 821: ... MSS configurator when the Libero SoC project is created The following steps are required 25 2 1 1 Step 1 Instantiate the SmartFusion2 MSS component into the Libero project and configure enable disable the peripherals using MSS configurator as required 25 2 1 2 Step 2 Double click FIC_2 Peripheral Initialization or right click FIC_2 and select Configure as shown in the following figure Figure 358 ...

Page 822: ...IC_2 Configurator 25 2 1 3 Step 3 Select either or both check boxes as required If MSS DDR is selected the FIC_2 Configurator shows the graphical illustration of the connectivity between the FIC_2 APB master and MSS DDR APB slave through CoreSF2Config as shown in the following figure Figure 360 FIC_2 Configuration for MSS DDR ...

Page 823: ...strated in FIC_2 configurator The following figure shows the connectivity between APB configuration interfaces of the SERDES and DDR subsystems both are selected Figure 361 FIC_2 Configuration for MSS DDR FDDR and SERDES If System Builder is used for creating the design CoreSF2Config is Instantiated and connections are made automatically ...

Page 824: ...gn when opened in SmartDesign Figure 362 MSS DDR Design with APB Configuration Interface FIC_2 APB master signals are shown in the boxes outlined in red while MSS DDR APB slave signal are shown in the boxes outlined in blue These signals are connected toCoreSF2Config In addition to APB configuration signals CoreSF2Config has a few other signals CONFIG_DONE CLR_INIT_DONE and INIT_DONE that are conn...

Page 825: ...Interface Signals The signals in the boxes outlined in red show the CoreSF2Config mirrored APB slave port that should be connected to the APB slave port of the SERDES block to be configured If you open this component in SmartDesign the canvas shows a hierarchical view of the design components for example CoreSF2Configand CoreSF2Reset with APB configuration interfaces as shown in Figure 362 page 79...

Page 826: ... error If the error is a single bit error checksum bits determine which bit contains the error EDAC algorithms implemented in SmartFusion2 SOC devices are designed to detect all two bit errors and correct all single bit errors within a single word Figure 365 EDAC in Write Mode When data is written to a storage element in memory through EDAC checksum bits are generated based on the input data patte...

Page 827: ...he data width ranges and the corresponding checksum bit widths 26 2 Configuration The EDAC architecture is implemented to protect different types of memories The data and checksum bit widths of the EDAC change according to the memory specifications Refer to the following chapters for EDAC configurations for specific types of memories eSRAM Embedded SRAM eSRAM Controllers Internal FIFOs of the Ethe...

Page 828: ...configurator options GUI available in the MSS The SECDED configurator dialog box is organized as follows EDAC_ERROR BUS This is the EDAC_ERROR bus signal to the FPGA fabric This signal can be used to expose the error bus to the fabric for monitoring EDAC_ENABLE EDAC_ENABLE can be used to enable the EDAC functionality for each of the following blocks eSRAM0 eSRAM1 Cache Ethernet MAC Tx and Rx RAMS ...

Page 829: ...le the MSS DDR MDDR ECC interrupts Figure 368 EDAC in Read Mode Reading From Memory The values entered in the configurator will be exported into the programming files for programming the flash bits that control the EDAC functionality The flash bits are loaded in the system registers at power up or when the DEVRST_N external pad is asserted deasserted ...

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