System Register Block
UG0331 User Guide Revision 15.0
681
0x178
RO-P
SYSRESET_
N
User Configuration Register 1
0x17C
RO-P
SYSRESET_
N
User Configuration Register 2
0x180
RO-P
SYSRESET_
N
User Configuration Register 3
0x184
RO-P
SYSRESET_
N
Size of memory protected from
fabric master
0x188
RO-P
SYSRESET_
N
Base address which is protected
from fabric master
0x18C
RO-P
SYSRESET_
N
MSS GPIO Definition Register
0x190
SW1C
SYSRESET_
N
Status of 1-bit SECDED error
detection and correction, 2-bit
SECDED error detection for
eSRAM0, eSRAM1, MAC, USB,
and CAN
0x194
SW1C
SYSRESET_
N
MSS Internal Status Register
0x198
SW1C
SYSRESET_
N
MSS External Status Register
0x19C
SW1C
PORESET_N Watchdog Time out event
register
0x1A0
W1P
SYSRESET_
N
Clear MSS counters
0x1A4
W1P
SYSRESET_
N
Clears 16-bit counter value in
eSRAM0, eSRAM1, MAC, USB,
and CAN corresponding to
count value of EDAC 1-bit and
2-bit errors
0x1A8
W1P
SYSRESET_
N
Flush Control Register
0x1AC
W1P
SYSRESET_
N
MAC Statistics Clear Control
Register
n is 0 to 56
0x1B0 to
0x290
RW-P
Register
PORESET_N I/O MUXCELL Configuration
Register
Table 650 •
SYSREG
(continued)
Register Name
Addr.
Offset
Register
Type
Flash
Write
Protect
Reset Source Description