MMUART Peripherals
UG0331 User Guide Revision 15.0
482
13.2.4.3.2 Auto Baud Rate Update FSM
The following figure describes the receiving LIN FSM. The FSM simply follows through by parsing the
break and sync fields, and then auto-updating the integer and fractional baud rate divisor register before
returning to idle.
Figure 190 •
LIN Receive FSM
13.2.4.4 RZI Modulation and Demodulation
The RZI modulation/demodulation blocks are intended to allow for IrDA serial infrared (SIR)
communications. The SIR specification uses RZI signaling for improving the peak power to average
power ratio in low rate wireless applications such as remote controls. RZI modulation scheme, a logic 0 is
represented as an infrared light pulse, as shown in the following figure. A logic zero is represented as a
3/16
th
high pulse, while no pulse in a given baud rate bit time equates to logic 1. UART 16x over-
sampling, start and stops bits are used. Modifications to a standard UART consist of adding an IrDA
modulator and demodulator in the TxD and RxD signal paths.
Figure 191 •
RZI Modulation
RZI demodulation takes pulses that are 3/16
th
of a baud rate clock long and transforms it to the standard
non-return to zero (NRZ) UART signal, which is then fed into the main UART Rx blocks. Similarly, RZI
modulation takes the outgoing UART NRZ Tx signal and creates 3/16
th
pulses out.
13.2.4.4.1 RZI to NRZ Demodulation
The RZI to NRZ demodulator looks for High to Low transitions on the input, marking each one as an RZI
pulse for applications such as IrDA. As High to Low transitions are detected, it is important to have any
noise suppressed before entering the demodulator. The input filter block (refer to the
page 479) of the MMUART is used to suppress noise.
However, true IrDA compliant optical transceivers should perform noise suppression and supply the
MMUART with noise free digital signals as per the IrDA specification.
Falling Edge Detected
Less than 11 zero Tbits in a
Row Detected
11 zero Tbits in a Row Detected,
LINBI Set
5 Falling Edges Detected,
LINSI Set,
Update Divisor Registers
Idle
Break
Count
Sync
Count
Start
Bit
Stop
Bit
Transmitter
Output
Data Bits
TxD
Bit Period
3/16 Bit Period
0
1
0
1
0
1
0
1
0
1