Peripheral DMA
UG0331 User Guide Revision 15.0
269
9.2.3
Initialization
To initiate and setup DMA transactions, PDMA has to be initialized. The initialization process starts with a
reset sequence followed by Channel configuration and interrupt configuration.
9.2.3.1
Reset
The PDMA registers are reset on power-up. The PDMA can be reset by configuring the following
•
Bit 5 of SOFT_RESET_CR system register.
•
Bit 5 of the CHANNEL_x_CONTROL register for channel reset.
9.2.3.2
Channel Configuration
Before configuring each PDMA channel, the round robin weight is specified if needed, using the
MASTER_WEIGHT_CR register or configuring the AHB bus matrix in Libero SoC.
To configure each PDMA channel, following fields of the channel control register has to be set:
•
Peripheral select - bits[26:23] of CHANNEL_x_CONTROL
•
No. of wait states - bits[21:14] of CHANNEL_x_CONTROL
•
Source and/or destination address increment - bits[13:10] of CHANNEL_x_CONTROL
•
Channel priority - bit 9 of CHANNEL_x_CONTROL
•
Interrupt enable - bit 6 of CHANNEL_x_CONTROL
•
Transfer size - bits [3:2] of CHANNEL_x_CONTROL
•
Direction - bit 1 of CHANNEL_x_CONTROL
•
Select the data Transfer type - bit 0 of CHANNEL_x_CONTROL
9.2.3.3
Interrupt
To use PDMA interrupt to Cortex-M3, Bit 8 of INTERRUPT_ENABLE0 register (located at address
0x40006000) has to be set. The PDMA Interrupt signal is also mapped to the dedicated interrupt signal
MSS_INT_M2F[8] of the fabric interface interrupt controller (FIIC). This is to interrupt the user logic
instantiated in the FPGA.
To determine transfer complete interrupt for each channel, the BUFFER_STATUS_x register bits[1:0] has
to be monitored. The bit 7 and bit 8 of CHANNEL_x_CONTROL register are used to clear the transfer
complete interrupts of the channel.
9.2.4
Details of Operations
After initialization, the PDMA is ready to function in any one of following transfer modes:
•
Peripheral to Memory Transfers/Memory to Memory Transfers
•
Posted APB Writes
9.2.4.1
Peripheral to Memory Transfers/Memory to Memory Transfers
For peripheral to memory or peripheral to memory transfer, the DMA transfer starts if
BUFFER_A_TRANSFER_COUNT or BUFFER_B_TRANSFER_COUNT is non-zero.
Before the transfer the source address (CHANNEL_x_BUFFER_A_SRC_ADDR) and destination
address (CHANNEL_x_BUFFER_B_DST_ADDR) of a channel are configured; then write to one of the
transfer count registers to begin the DMA transaction. Alternatively, firmware can also write to the control
register first and turn pause on, if needed, then turn it off later.
If the PAUSE bit in the
register is set, when you write a non-zero value to
BUFFER_A_TRANSFER_COUNT or BUFFER_B_TRANSFER_COUNT, then the DMA transaction
waits until PAUSE is cleared.
If bidirectional DMA of peripheral to memory (receive) and memory to peripheral (transmit) is desired,
two channels must be programmed appropriately. In particular, the TRANSFER_SIZE fields in both the
registers must be programmed identically.
Channels can be assigned to peripherals or memory arbitrarily. For example, to receive only DMA data
from one of the SPI ports, only one channel is required. In this case, the DIR bit in the