Cortex-M3 Processor (Reference Material)
UG0331 User Guide Revision 15.0
62
3.6.4.4.3
Restrictions
In these instructions:
•
Rn
must not be PC.
•
Rt
must not be SP and must not be PC.
3.6.4.4.4
Condition Flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access.
3.6.4.5
LDR, PC-relative
Load register from memory.
3.6.4.5.1
Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label
; Load two words
where:
•
type
is one of:
•
B: unsigned byte, zero extend to 32 bits.
•
SB: signed byte, sign extend to 32 bits.
•
H: unsigned halfword, zero extend to 32 bits.
•
SH: signed halfword, sign extend to 32 bits.
•
-: omit, for word.
•
cond
is an optional condition code, see
•
Rt
is the register to load or store.
•
Rt2
is the second register to load or store.
•
label
is a PC-relative expression. See
3.6.4.5.2
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is specified
by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords
can either be signed or unsigned. See
label
must be within a limited range of the current instruction. The following table shows the possible
offsets between
label
and the PC.
Note:
You might have to use the .W suffix to get the maximum offset range. See
Table 32 •
Offset Ranges
Instruction type
Offset range
Word, halfword, signed halfword, byte, signed byte
-4095 to 4095
Two words
-1020 to 1020