MMUART Peripherals
UG0331 User Guide Revision 15.0
498
13.4.11 Line Status Register (LSR)
4
Loop
R/W
0
In the Loopback mode, MMUART_x_TXD is set to 1. The
MMUART_x_RXD, MMUART_x_DSR, MMUART_x_CTS,
MMUART_x_RI, and MMUART_x_DCD inputs are disconnected. The
output of the transmitter shift register is looped back into the receiver shift
register. The modem control outputs (MMUART_x_DTR,
MMUART_x_RTS, MMUART_x_OUT1, and MMUART_x_OUT2) are
connected internally to the modem control inputs, and the modem control
output pins are set as 1. The transmitted data is immediately received,
allowing Cortex-M3 processor to check the operation of the MMUART_x.
The interrupts are operating in the Loopback mode.
0: Disabled (default)
1: Local loopback enabled
The local loopback mode has priority over the remote loopback modes.
LOOPBACK is only implemented in basic UART mode. It does function in
LIN IRDA or Smart card modes.
3
OUT2
R/W
0
Controls the output2 (OUT2) signal. Active Low
0: OUT2n is set to 1 (default)
1: OUT2n is set to 0
2
OUT1
R/W
0
Controls the output1 (OUT1) signal. Active Low
0: OUT1n is set to 1 (default)
1: OUT1n is set to 0
1
RTS
R/W
0
Controls the request to send (MMUART_x_RTS) signal. Active Low
0: RTSn is set to 1 (default)
1: RTSn is set to 0
0
DTR
R/W
0
Data terminal ready (MMUART_x_DTR) output. Active Low
0: DTRn output is set to 1 (default)
1: DTRn output is set to 0
Table 482 •
LSR
Bit
Number
Name
R/W
Reset
Value
Description
7
FIER
R
0
This bit is set when there is at least one parity error, framing error, or break
indication in the FIFO. FIER is cleared when Cortex-M3 processor reads
the LSR, if there are no subsequent errors in the FIFO.
6
TEMT
R
1
Transmit empty (TEMT). This bit is set to 1 when both the transmitter
FIFO and shift registers are empty.
5
THRE
R
1
Transmitter holding register empty (THRE). Indicates that the MMUART_x
is ready to transmit a new data byte. THRE causes an interrupt to the
Cortex-M3 processor when bit 1 (ETBEI) in the interrupt enable register is
1. This bit is set when the Tx FIFO is empty. It is cleared when at least one
byte is written to the Tx FIFO.
4
BI
R
0
Break interrupt (BI). Indicates that the receive data is at 0 longer than a full
word transmission time (start bit + data bits + stop bits). BI is
cleared when Cortex-M3 processor reads the line status register (
This error is revealed to the Cortex-M3 processor when it is associated
character is at the top of the FIFO. When break occurs, only one zero
character is loaded into the FIFO.
Table 481 •
MCR
(continued)
Bit
Number
Name
R/W
Reset
Value
Description