LSI LSI53C1000, Technical Manual

Page: 368 / 384

IX-4 Index
assert
SCSI (Cont.)
MSG/ signal (MSG) 4-37 , 4-39
REQ/ signal (REQ) 4-37 , 4-39
RST/ signal (RST) 4-28
SEL/ signal (SEL) 4-37 , 4-39
asynchronous information protection 2-25
enable 4-99
asynchronous SCSI
receive 2-38
send 2-37
aux_current 4-19
B
base address register
four (BAR4) 4-11
one (BAR1) 2-4 , 4-10
three (BAR3) 4-11
two (BAR2) 4-10
zero (BAR0) 2-4 , 4-9
BCH 2-25
bidirectional 3-2
signals 6-5 , 6-6
BIOS 2-3
bits used for parity control and generation 2-34
block move 2-10
instructions 5-4
bridge support extensions (BSE[7:0]) 4-20
burst
length (BL[1:0]) 4-61
length bit 2 (BL2) 4-57
opcode fetch enable (BOF) 4-63
size selection 2-7
bus
command and byte enables 3-6
fault (BF) 4-40 , 4-64
byte
count 5-39
empty in DMA FIFO (FMT[7:0]) 4-51
full in DMA FIFO (FFL[7:0]) 4-51
C
C_BE[3:0]/ 2-3
C_BE[7:0]/ 3-6
cache line size
(CLS) 2-8 , 4-7
enable (CLSE) 2-8 , 4-65
register 2-7 , 2-10
cache mode, See PCI cache mode 2-10
call instruction 5-28
Cap_ID (CID[7:0]) 4-18
capabilities pointer (CP[7:0]) 4-15
capability ID register 4-18
carry test 5-31
chained block moves 2-55 , 2-57
chained mode (CHM) 4-30
change bus phases 2-18
chip
control 0 (CCNTL0) 4-89
control 1 (CCNTL1) 4-91
test five (CTEST5) 2-7 , 4-56
test four (CTEST4) 2-34 , 4-55
test one (CTEST1) 4-51
test six (CTEST6) 4-57
test three (CTEST3) 2-9 , 2-12 , 4-53
test two (CTEST2) 4-52
test zero (CTEST0) 4-51
CHMOV 2-55
class code register 4-7
clear DMA FIFO (CLF) 2-51 , 4-54
clear instruction 5-16
clear SCSI FIFO (CSF) 2-51 , 4-86
CLK 3-5
clock 3-5
quadrupler 2-30
command register 2-12 , 4-3
compare
data 5-32
phase 5-32
configuration
read command 2-6
space 2-3
write command 2-6
configured
as I/O (CIO) 4-52
as memory (CM) 4-52
connected (CON) 4-28 , 4-47
CRC 1-4 , 2-23
control and generation 2-34
disable checking 4-115
disable protocol checking 4-115
options 2-33
CRC-32 1-4
cumulative SCSI byte count (CSBC) 4-114
current
function of input voltage 6-9
function of output voltage 6-10
cycle frame 3-7
cyclic redundancy check 1-4
D
D0 2-63
D1 2-63
D1_Support (D1S) 4-19
D2 2-64
D2_Support (D2S) 4-19
D3 2-64
D3cold 2-64
D3hot 2-64
DACs 2-21
data
(DATA[7:0]) 4-21
compare mask 5-32
compare value 5-33
parity error reported (DPR) 4-6
paths 2-37
structure address (DSA) 4-45
data_scale (DSCL) 4-20
data_select (DSLT) 4-20
DC characteristics 6-1
default download mode 2-61
destination
address 5-24
I/O-memory enable (DIOM) 4-62
detected parity error (from slave) (DPE) 4-5
device
ID (DID[15:0]) 4-3
select 3-7
specific initialization (DSI) 4-19