LSI LSI53C1000, Technical Manual

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SCSI Registers 4-87
Registers: 0x50–0x51
SCSI Input Data Latch (SIDL)
Read Only
SIDL SCSI Input Data Latch [15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery.
Asynchronous Data received from the SCSI bus can be
read from this register. When receiving asynchronous
SCSI data, the data flows into this register and out to the
host FIFO. This register differs from the
SCSI Bus Data
Lines (SBDL) register; the SCSI Input Data Latch (SIDL)
contains latched data and the SCSI Bus Data Lines
(SBDL) always contains exactly what is currently on the
SCSI data bus. Reading this register causes the SCSI
parity bit to be checked, and causes a parity error
interrupt if the data is invalid. The power-up values are
indeterminate.
Register: 0x52
SCSI Test Four (STEST4)
Read Only
SMODE[1:0] SCSI Mode [7:6]
These bits contain the encoded value of the SCSI
operating mode that is indicated by the voltage level
sensed at the DIFFSENS pin. The incoming SCSI signal
goes to a pair of analog comparators that determine the
voltage window of the DIFFSENS signal. These voltage
windows indicate LVD, SE, or HVD operation. The bit
values are defined in the following table. When the HVD
mode is detected, all of the LSI53C1000 3-state outputs
go to the high impedance state.
15 0
SIDL
x x x x x x x x x x x x x x x x
7 6 5 0
SMODE[1:0] R
x x 0 0 0 0 0 0