PCI Functional Description
2-15
Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords:
Read Example 3 – Burst = 16 Dwords, Cache Line Size = 8 Dwords:
A to B:
MRL (6 bytes)
A to C:
MRL (13 bytes)
A to D:
MRM (17 bytes)
C to D:
MRM (5 bytes)
C to E:
MRM (21 bytes)
D to F:
MRM (32 bytes)
A to H:
MRM (32 bytes)
MRM (32 bytes)
MRM (17 bytes)
A to G:
MRM (32 bytes)
MRM (32 bytes)
MR (2 bytes)
A to B:
MRL (6 bytes)
A to C:
MRL (13 bytes)
A to D:
MRL (17 bytes)
C to D:
MRL (5 bytes)
C to E:
MRM (21 bytes)
D to F:
MRM (32 bytes)
A to H:
MRM (64 bytes)
MRL (17 bytes)
A to G:
MRM (64 bytes)
MR (2 bytes)
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...