LSI LSI53C1000, Technical Manual

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SCSI Registers 4-61
Registers: 0x34–0x37
Scratch Register A (SCRATCHA)
Read/Write
SCRATCHA Scratch Register A [31:0]
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only register read/write
and Memory Moves into the SCRATCH register alter its
contents. The power-up value of this register is
indeterminate.
A special mode of this register is enabled by setting the
PCI Configuration Info Enable bit in the
Chip Test Two
(CTEST2) register. If this bit is set, Scratch Register A
(SCRATCHA) returns bits [31:10] of the PCI Base
Address Register One (BAR1) (MEMORY) in bits [31:10].
Bits [9:0] of SCRATCH A will always return zero in this
mode. Writes to the SCRATCHA register are unaffected.
Clearing the PCI Configuration Info Enable bit causes the
SCRATCH A register to return to normal operation.
Register: 0x38
DMA Mode (DMODE)
Read/Write
BL[1:0] Burst Length [7:6]
These bits control the maximum number of Dwords
transferred per bus ownership, regardless of whether the
transfers are back-to-back, burst, or a combination of
both. This value is also independent of the width (64-bit
or 32-bit) of the data transfer on the PCI bus. The
LSI53C1000 asserts the Bus Request (PCIREQ/) output
when the DMA FIFO can accommodate a transfer of at
least one burst threshold of data. Bus Request
(PCIREQ/) is also asserted during start-of-transfer and
31 0
SCRATCHA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
BL[1:0] SIOM DIOM ERL ERMP BOF MAN
0 0 0 0 0 0 0 0