LSI LSI53C1000, Technical Manual

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2-28 Functional Description
– Bit 6, AIPCKEN (AIP Checking Enable), is set to enable checking
of the upper byte lane of protection information during
Command, Status, and Message Phases.
– Bits [5:4] are reserved.
– Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer
Edge) is set to add a clock of data hold to synchronous DT SCSI
transfers on the DT edge.
– Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST Transfer
Edge) is set to add a clock of data hold to synchronous DT or
ST SCSI transfers on the ST edge. This bit impacts both ST and
DT transfers as it affects data hold to the ST edge.
– Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT Transfer
Edge) is set to add a clock of data setup to synchronous DT
SCSI transfers on the DT edge. This bit only impacts DT
transfers as it affects data setup to the DT edge.
– Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST Transfer
Edge) is set to add a clock of data setup to synchronous DT or
ST SCSI transfers on the ST edge. This bit impacts both ST and
DT transfers as it affects data setup to the ST edge.
Note: The XCLKH_DT, XCLKH_ST, XCLKS_DT, and XCLKS_ST
bits do not affect CRC timings.
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The AIP Control Zero (AIPCNTL0) register:
– Bits [7:3] are reserved.
– Bit 2, AIPERR_LIVE (AIP Error Status Live), represents the live
error status for the AIP checking logic. This is not a latched
value. Use this value for diagnostic purposes only.
– Bit 1, AIPERR (AIP Error Status), represents the error status for
the AIP checking logic. Use this bit only when AIP checking is
enabled.
– Bit 0, PARITYERR (Parity Error), represents the error status for
the parity error.
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The AIP Control One (AIPCNTL1) register:
– Bits [7:4] are reserved.
– Bit 3, DISAIP (Disable AIP Code Generation), disables the AIP
code generation on the SCSI bus.