LSI LSI53C1000, Technical Manual

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PCI Functional Description 2-7
2.1.2.10 Memory Read Multiple Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch multiple cache lines
before disconnecting. The LSI53C1000 supports PCI Memory Read
Multiple functionality and issues Memory Read Multiple commands on
the PCI bus when the Read Multiple mode is enabled. This mode is
enabled by setting bit 2 (ERMP) of the
DMA Mode (DMODE) register. If
the cache mode is enabled, a Memory Read Multiple command is issued
on all read cycles, except opcode fetches, when the following conditions
are met:
•
The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)
register) is set.
•
The ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE)
register) is set.
•
The Cache Line Size (CLS) register contains a legal burst size value
(8, 16, 32, 64, or 128 Dwords) that is less than or equal to the
DMODE burst size.
•
The transfer crosses a cache line boundary.
When these conditions are met, the chip issues a Memory Read Multiple
command instead of a Memory Read during all PCI read cycles.
Burst Size Selection – The Read Multiple command reads in multiple
cache lines of data during a single bus ownership. Revision 2.2 of the
PCI specification specifies the number of cache lines to read as a
multiple of the cache line size. The logic selects the largest multiple of
the cache line size based on the amount of data to transfer. The
maximum allowable burst size is determined from the
DMA Mode
(DMODE) burst size bits and the Chip Test Five (CTEST5) register, bit 2.
2.1.2.11 Dual Address Cycles (DAC) Command
When 64-bit addressing is required, the LSI53C1000 performs DAC, per
the PCI 2.2 specification. If any of the selector registers contain a
nonzero value, a DAC is generated.