LSI LSI53C1000, Technical Manual

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4-96 Registers
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
MMWS Memory Move Write Selector [31:0]
This register supplies AD[63:32] during data write
operations during Memory-to-Memory Moves and
absolute address STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
Chip Test Two
(CTEST2) register. If this bit is set, the MMWS register
returns bits [31:0] of the SCRIPT RAM PCI Base Address
Register Four (BAR4) (SCRIPTS RAM) in bits [31:0] of
the MMWS register when read. In this mode, writes to the
MMWS register affect no change. Clearing the PCI
Configuration Info Enable bit causes the MMWS register
to return to normal operation.
Registers: 0xA8–0xAB
SCRIPT Fetch Selector (SFS)
Read/Write
SFS SCRIPT Fetch Selector [31:0]
This register supplies AD[63:32] during SCRIPT Fetches
and Indirect Fetches (excluding Table Indirect Fetches).
This register can be loaded automatically using a 64-bit
jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
Chip Test Two
(CTEST2) register. If this bit is set, bits [23:16] of this
register return the PCI Revision ID (RID) register value
and bits [15:0] return the PCI Device ID register value
when read.
31 0
MMWS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
SFS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0