LSI LSI53C1000, Technical Manual

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SCSI Functional Description 2-47
SCSI-type and DMA-type interrupts may occur simultaneously, so in
some cases both SIP and DIP may be set. To avoid missing a SCSI
interrupt the SIST0 and SIST1 registers should be read before the
DSTAT register is read.
When set, the SIRQD bit in ISTAT1 disables the INTA/ pin for the SCSI
function. The interrupt is not lost or ignored but is merely masked at the
pin. If the INTA/ pin is already asserted when SIRQD is set, the INTA/
pin will remain asserted until the interrupt is serviced. Future interrupts
will be masked at the pin until SIRQD is cleared.
Note that the host can read ISTAT as the SCRIPTS code is writing to
ISTAT. In this case the data will be unstable, so the read should be
retried.
SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI
Interrupt Status One (SIST1) registers contain the status of SCSI-type
interrupts whether they are enabled in SCSI Interrupt Enable Zero
(SIEN0) and SCSI Interrupt Enable One (SIEN1) or not. Reading these
registers determines the conditions that caused the SCSI-type interrupt,
clears any bits that are set in SIST0 and SIST1, and clears the SIP bit
in
Interrupt Status Zero (ISTAT0) . Since the LSI53C1000 stacks
interrupts, SIST0 and SIST1 are not necessarily cleared after a read;
additional interrupts may still be pending.
If the LSI53C1000 is receiving data from the SCSI bus and a fatal
interrupt condition occurs, the chip attempts to send the contents of the
DMA FIFO to memory before generating the interrupt. Reading
SCSI
Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) will
clear the CRC Error bit (bit 7) in the CRC Control One (CRCCNTL1)
register.
If the LSI53C1000 is sending data to the SCSI bus and a fatal SCSI
interrupt condition occurs, data could remain in the DMA FIFO. To
determine if the DMA FIFO is empty, check the DMA FIFO Empty (DFE)
bit in
DMA Status (DSTAT) register. If this bit is cleared, set the CLF
(Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits before continuing.
The CLF bit is bit 2 in
Chip Test Three (CTEST3) register. The CSF bit
is bit 1 in SCSI Test Three (STEST3) register.