LSI LSI53C1000, Technical Manual

Page: 178 / 384

4-68 Registers
Registers: 0x3C–0x3F
Adder Sum Output (ADDER)
Read Only
ADDER Adder Sum Output [31:0]
This register contains the output of the internal adder,
and is used primarily for test purposes. The power-up
value for this register is indeterminate.
Register: 0x40
SCSI Interrupt Enable Zero (SIEN0)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status Zero
(SIST0) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts see Chapter 2, “Functional
Description.”
M/A SCSI Phase Mismatch - Initiator Mode;
SCSI ATN Condition - Target Mode
7
In the initiator mode, this bit is set when the SCSI phase
asserted by the target and sampled during SREQ/ does
not match the expected phase in the
SCSI Output Control
Latch (SOCL) register. This expected phase is
automatically written by SCSI SCRIPTS. In the target
mode, this bit is set when the initiator asserts SATN/. See
the Disable Halt on Parity Error or SATN/ Condition bit in
the
SCSI Control One (SCNTL1) register for more
information on when this status is actually raised.
CMP Function Complete 6
When set, this bit indicates the full arbitration and
selection sequence is completed.
31 0
ADDER
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
M/A CMP SEL RSL SGE UDC RST PAR
0 0 0 0 0 0 0 0