3-16
Signal Descriptions
3.8 Power and Ground Signals
describes the Power and Ground Signal group.
Table 3.14
Power and Ground Signals
Name
1
Bump
Type
Strength
Description
V
SS_IO
C3, C21, D4, D12, D20,
K10–14, L10–14, M4, M10–14,
M20, N10–14, P10–14, Y4,
Y12, Y20, AA3, AA21
G
N/A
Ground for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers, and other I/O
pins.
V
DD_IO
D7, D10, D14, D17, G4, G20,
K4, K20, P4, P20, U4, U20,
Y7, Y10, Y14, Y17
P
N/A
Power for PCI bus
drivers/receivers, SCSI bus
drivers/receivers, local memory
interface drivers/receivers, and
other I/O pins.
V
DD
_CORE B22, B23, D3, E4, Y13, AB3,
AB18, AB23, AC1
P
N/A
Power for core logic.
V
SS
_CORE
A22, D2, D21, F3, Y15, AA22,
AB19, AB2, AC2, AC21
G
N/A
Ground for core logic.
V
DD
_A
2
B2, C20
P
N/A
Power for analog cells (clock
quadrupler and DIFFSENS logic).
V
SS
_A
2
B20, C2
G
N/A
Ground for analog cells (clock
quadrupler and DIFFSENS logic).
V
DD
_Bias
A11, M22
P
N/A
Power for the RBIAS circuit.
RBIAS
M21
I
N/A
Used to connect an external
resistor to generate the bias
current used by LVDlink pads.
Resistor value should be 10.0 k
Ω
.
Connect the other end of the
resistor to V
DD
.
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...