6-26
Specifications
Table 6.24
Burst Opcode Fetch, 32-Bit Address and Data
Symbol
Parameter
66 MHz PCI
33 MHz PCI
Unit
Min
Max
Min
Max
t
1
Shared signal input setup time
3
–
7
–
ns
t
2
Shared signal input hold time
0
–
0
–
ns
t
3
CLK to shared signal output valid
2
6
2
11
ns
t
4
Side signal input setup time
5
–
10
–
ns
t
5
Side signal input hold time
0
–
0
–
ns
t
6
CLK to side signal output valid
2
6
2
12
ns
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...