LSI LSI53C1000, Technical Manual

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4-48 Registers
INTF Interrupt-on-the-Fly 2
This bit is asserted by an INTFLY instruction during
SCRIPTS execution. SCRIPTS programs do not halt
when the interrupt occurs. This bit can be used to notify
a service routine, running on the main processor while
the SCRIPTS processor is still executing a SCRIPTS
program. If this bit is set, when the
Interrupt Status Zero
(ISTAT0) register is read it is not automatically cleared. To
clear this bit, write a one to it. The reset operation is
self-clearing.
Note: If the INTF bit is set but SIP or DIP is not set, do not
attempt to read the other chip status registers. An
interrupt-on-the-fly must be cleared before servicing any
other interrupts indicated by SIP or DIP.
After it has been set, this bit must be written to one to clear
it.
SIP SCSI Interrupt Pending 1
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C1000. The
following conditions cause a SCSI interrupt to occur:
•
A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
•
An arbitration sequence completes
•
A selection or reselection time-out occurs
•
The LSI53C1000 is selected
•
The LSI53C1000 is reselected
•
A SCSI gross error occurs
•
An unexpected disconnect occurs
•
A SCSI reset occurs
•
A parity error is detected
•
The handshake-to-handshake timer expires
•
The general purpose timer expires
To determine which condition(s) caused the
interrupt, read the
SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.