SCSI Registers
4-83
Register: 0x4D
SCSI Test One (STEST1)
Read/Write
R
Reserved
[7:6]
DOSGE
Disable Outbound SCSI Gross Errors
5
When set, this bit disables all SCSI gross errors related
to outbound data transfers.
DISGE
Disable Inbound SCSI Gross Errors
4
When set, this bit disables all SCSI gross errors related
to inbound data transfers.
QEN
SCLK Quadrupler Enable
3
This bit, when set, powers up the internal clock
quadrupler circuit, which quadruples the SCLK 40 MHz
clock to the internal 160 MHz SCSI clock required for
Ultra2 and Ultra160 SCSI operation. When cleared, this
bit powers down the internal quadrupler circuit. Refer to
Chapter 2, “Functional Description,”
for information
concerning the operation of the quadrupler.
QSEL
SCLK Quadrupler Select
2
This bit, when set, selects the output of the internal clock
quadrupler as the internal SCSI clock. When cleared, this
bit selects the clock presented on SCLK as the internal
SCSI clock. Refer to
Chapter 2, “Functional Description,”
for information concerning the operation of the
quadrupler.
IRM[1:0]
Interrupt Routing Mode
[1:0]
The LSI53C1000 supports four different interrupt routing
modes. These modes are described in the following table.
Mode 0, the default mode, is compatible with RAID
upgrade products.
7
6
5
4
3
2
1
0
R
DOSGE
DISGE
QEN
QSEL
IRM[1:0]
0
0
0
0
0
0
0
0
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...