PCI and External Memory Interface Timing Diagrams
6-55
Figure 6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Write Cycle
(Cont.)
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
MAD
(Driven by LSI53C1000)
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
17
18
19
20 21
22
23
24
25
26
27
28
29 30
31
Byte Enable
16
32
33
Low Order
Address
Data In
Data Out
(Driven by Master)
(Driven by Master)
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...