PCI and External Memory Interface Timing Diagrams
6-29
Figure 6.19 Back to Back Read, 32-Bit Address and Data
t
4
t
1
t
3
t
1
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000)
GPIO1_MASTER/
(Driven by LSI53C1000)
REQ/
(Driven by LSI53C1000)
PAR
(Driven by LSI53C1000-
IRDY/
(Driven by LSI53C1000)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
t
1
t
6
t
3
AD[31:0]
(Driven by LSI53C1000-
C_BE[3:0]/
(Driven by LSI53C1000)
t
3
CMD
t
2
REQ64/
(Driven by LSI53C1000)
ACK64/
(Driven by LSI53C1000)
t
1
t
2
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000)
t
5
Data
In
Addr
Out
Data
In
Addr
Out
CMD
t
3
t
2
t
2
Addr; Target-Data)
Addr; Target-Data)
t
3
BE
BE
Out
In
Out
In
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...