4-20
Registers
DSCL
Data_Scale
[14:13]
The LSI53C1000 does not support the Data register.
Therefore, these two bits are always cleared.
DSLT
Data_Select
[12:9]
The LSI53C1000 does not support the Data register.
Therefore, these four bits are always cleared.
PEN
PME_Enable
8
The LSI53C1000 always returns zero for this bit to
indicate that PME assertion is disabled.
R
Reserved
[7:2]
PWS[1:0]
Power State
[1:0]
Bits [1:0] are used to determine the current power state
of the LSI53C1000. They are used to place the
LSI53C1000 in a new power state. Power states are
defined as:
See the
Section 2.5, “Power Management,”
for
descriptions of the Power Management States.
Register: 0x46
Bridge Support Extensions (PMCSR_BSE)
Read Only
BSE
Bridge Support Extensions
[7:0]
This register indicates PCI Bridge specific functionality.
The LSI53C1000 always returns 0x00.
0b00
D0
0b01
D1
0b10
D2
0b11 D3 hot
7
0
BSE
0
0
0
0
0
0
0
0
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...