LSI LSI53C1000, Technical Manual

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4-54 Registers
CLF Clear DMA FIFO 2
When this bit is set, all data pointers for the DMA FIFO
are cleared. Any data in the FIFO is lost. After the
LSI53C1000 successfully clears the appropriate FIFO
pointers and registers, this bit automatically clears.
Note: This bit does not clear the data visible at the bottom of the
FIFO.
R Reserved 1
WRIE Write and Invalidate Enable 0
This bit, when set, causes the issuing of Write and
Invalidate commands on the PCI bus whenever legal.
The Write and Invalidate Enable bit in the PCI
Configuration
Command register must also be set for the
chip to generate Write and Invalidate commands.
Registers: 0x1C–0x1F
Temporary (TEMP)
Read/Write
TEMP Temporary [31:0]
This 32-bit register stores the Return instruction address
pointer from the Call instruction. The address pointer
stored in this register is loaded into the
DMA SCRIPTS
Pointer (DSP) register when a Return instruction is
executed. This address points to the next instruction to
execute. Do not write to this register while the
LSI53C1000 is executing SCRIPTS.
During any Memory-to-Memory Moves operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
31 0
TEMP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0